Network of computing devices including a repeater for distributed arbitration digital data buses

ABSTRACT

The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches ( 40 ) for distributed arbitration digital data buses ( 52, 54, 56  and  58 ) to which devices ( 62, 64, 66, 68, 72  and  74 ) connect in parallel. The bus repeater/switch ( 40 ) includes a plurality of bus interface cards (48) that are connected to the distributed arbitration buses ( 52, 54, 56  and  58 ) for receiving signals from and transmitting signals to devices ( 62, 64, 66, 68, 72  and  74 ) connected thereto. The bus interface cards ( 48 ) connect to a control card ( 44 ) which allows signals from one of the sharing buses ( 52, 54  or  56 ) to be exchanged with the shared bus ( 58 ). The bus switch ( 40 ) also includes selector switch ( 84  or  88 ) for choosing which particular one of the sharing buses ( 52, 54  or  56 ) exchanges digital data signals with the shared bus ( 58 ). The bus switch ( 40 ) responds to signals on the distributed arbitration buses ( 52, 54, 56  and  58 ) and to phases of the protocol for those signals so that its presence between pairs of buses ( 52 - 58, 54 - 58  or  56 - 58 ) is imperceptible to devices ( 62, 64, 66, 68, 72  and  74 ) connected thereto.

TECHNICAL FIELD

[0001] The present invention relates generally to the technical field ofdigital computers and, more particularly, to electronic devices forswitching among fully bidirectional digital data buses interconnectingdigital computing devices.

BACKGROUND ART

[0002] Data buses are used throughout digital computer systems forcommunicating signals from one portion of the system to another. Digitaldata buses are used within microprocessor chips to communicate signalsbetween different functional elements included in central processingunits (“CPUs”) of microprocessors or microcomputers, in floating pointcoprocessor chips, in memory management unit chips, etc. Within adigital computer but outside such integrated circuit chips, digital databuses communicate signals among those chips and between them and otherassemblies included within the computer such as Random Access Memories(“RAM”), Read Only Memories (“ROM”) and/or peripheral deviceinput/output circuits. External to the computer, digital data busescommunicate signals between it and peripheral devices such as keyboards,display devices, printers, modems, disk drives of various differenttypes and/or tape drives.

[0003] Because of the widespread use of digital data buses throughoutdigital computer systems, myriad different types of buses have beendeveloped over the years together with extremely sophisticated protocolsgoverning the signaling process by which data is transferred over thebus between two devices such as between a digital computer and aperipheral device, e.g. a disk drive or a tape drive. For example,digital data buses and protocols have been developed in which onedevice, e.g. the digital computer or a portion of the digital computeridentified variously by the terms channel or controller, is permanentlyassigned control of the data bus for transfers of data both to and fromthe peripheral device. For this type of bus, frequently the device thatcontrols the bus is referred to as the bus master and the other devicesconnected to the bus are referred to as slaves. Other digital data busesand protocols have been developed in which a bus arbitration circuitseparate from all peripheral devices assigns control of the data bus toone or the other of two intercommunicating devices, e.g. either thedigital computer or the peripheral device. This type of bus protocol isoften called multi-master with centralized arbitration.

[0004] A widely used digital data bus having a sophisticated protocolfor exchanging data between devices is defined by the American NationalStandards Institute (“ANSI”) X3.131-1986 standard which is incorporatedherein by reference. This ANSI standard digital data bus is knowncolloquially as the Small Computer System Interface (“SCSI”) bus. TheSCSI bus differs from most prior data buses in several ways. First,devices connect to the SCSI bus in such a way that none of the signallines in the bus pass through any circuitry in any devices. Rather, eachdevice applies its signals to each of the SCSI bus signal lines. Theother devices then receive those signals via the bus. Second, the SCSIbus permits distributed arbitration in which all the devices thatarbitrate for the bus at a particular time resolve among themselveswhich of them will receive control of the bus. This contrasts with themulti-master bus with centralized arbitration.

[0005] As defined by the ANSI standard, the SCSI bus includes a DATA BUShaving eight bidirectional data signal lines and an optionalbidirectional data parity signal line, a termination power line, groundlines, and a set of nine (9) control signal lines, some of which arebidirectional. The 9 control signal lines of the SCSI bus are a Busy(“BSY”) signal line, a Select (“SEL”) signal line, a Control/Data(“C/D”) signal line, an Input/Output (“I/O”) signal line, a Message(“MSG”) signal line, a Request (“REQ”) signal line, an Acknowledge(“ACK”) signal line, an Attention (“ATN”) signal line, and a Reset(“RST”) signal line. Examples of the signals that may be transmittedover these various signal lines are illustrated in FIG. 1.

[0006] In designing devices to be interconnected by a SCSI bus, one oftwo mutually incompatible conventions may be selected for the electricalsignals present on the bus. These two alternative electrical conventionsare respectively identified as “single-ended,” which has a maximum totalcable length of 6 meters, and “differential,” which has a maximum totalcable length of 25 meters. Devices having a single-ended SCSI businterface circuit and those having a differential SCSI bus interfacecircuit cannot be simultaneously connected to the same SCSI bus.Accordingly, all devices connected to a particular SCSI bus must beeither single-ended or differential. The signal protocol fortransferring signals over a SCSI bus remains the same regardless ofwhich of these two, mutually exclusive electrical conventions is chosento implement the bus.

[0007] In accordance with the ANSI SCSI bus standard for thesingle-ended convention, the control, data and parity signal lines inthe buses are true or asserted when in their low voltage state and arefalse or negated when in their high voltage state. For the differentialconvention, assertion is the condition in which the voltage on a “−”signal line is lower than that on the associated “+” signal line.Negation reverses this relationship with the voltage on the “−” signalline becoming higher than that on the “+” signal line. In thedescription that follows, when a device is said to “assert” (“negate”)name(s) of signal line(s), this means the device asserts (negates) thesignal(s) it applies to that line (those lines) in the SCSI bus.

[0008] In both of these conventions, two termination resistor networks,positioned at opposite ends of the bus and connected to all the SCSI bussignal lines, bias them to their unasserted state when no signal ispresent on the line. Consequently, all the signal lines respectivelyremain in their unasserted state unless a device connected to the SCSIbus asserts one or more of them. Furthermore, the BSY and RST signallines of the SCSI bus, which are “wire-OR” signal lines, may be drivensimultaneously by more than one device connected to the bus. Thus, forthe BSY and RST signal lines, negation by a device does not mean thatthe BSY or RST line is actually negated. Rather negation by a devicemeans merely that the device ceases to assert the signal it applies tothe BSY or RST line.

[0009] Each device connected to a SCSI bus is assigned a unique addresson the bus. A device's address on the SCSI bus corresponds to one of thebus' eight DATA BUS signal lines. Thus, a maximum of eight devices, eachdevice being assigned one of the device addresses 0 through 7, may beconnected to a SCSI bus with the address of each such devicecorresponding to one of the eight DATA BUS' signal lines. In thedescription which follows, when a device is said to assert an address onthe SCSI bus, this means that it asserts the signal on the DATA BUS linecorresponding to that address.

[0010] When two SCSI devices communicate over the bus, one device actsan initiator of the exchange and the other acts as its target device. Aninitiating device sends commands to a target and the target deviceperforms them. Particular devices, e.g. a digital computer, a diskdrive, a tape drive, etc., usually have fixed roles as either aninitiator or as a target. However, in accordance with the SCSI standard,under certain circumstances some devices may be able to selectivelyoperate either as an initiator or as a target. Furthermore, an initiatorand a target may, by mutual agreement, execute a command by having thetarget release the bus following receipt of the command but beforecompleting it. Under such circumstances, the target subsequentlyarbitrates for the bus and then reselects the initiator to completeexecution of the command.

[0011] Certain SCSI bus functions are assigned to the initiator andcertain are assigned to the target. An initiator may contend for controlof the SCSI bus and upon acquiring control select a particular target,or conversely. After selection or reselection has occurred, the targetalways controls the exchange of data from the initiator. A target mayrequest the transfer from the initiator of COMMAND, DATA, STATUS orother information over the DATA BUS lines.

[0012] Information transfers over the data lines of the SCSI bus areinterlocked and follow a defined REQ/ACK handshake protocol. One byte ofinformation may be transferred with each REQ/ACK handshake. There aretwo modes of interlocking that may be selected. In an “asynchronous”mode, the transfer of each byte of data must be acknowledged before thenext byte may be transferred. In a “synchronous” mode, up to eight bytesof data may be transferred before an acknowledgement must occur.

[0013] Under the signaling protocol for communicating over the SCSI bus,there are eight distinct phases: a BUS FREE phase, an ARBITRATION phase,a SELECTION phase, a RESELECTION phase, and four different informationexchange phases, i.e. a COMMAND phase, a DATA phase, a STATUS phase, anda MESSAGE phase. Under the ANSI standard, some of the protocols forthese 4 information exchange phases may operate in various differentways depending upon the options that have been chosen from the SCSIstandard in designing the two communicating devices.

[0014]FIG. 1 depicts the signals present on the nine control signallines and the DATA BUS signal lines in the SCSI bus. As illustrated inFIG. 1, the BUS FREE phase of SCSI bus operation, depicted to the leftof dashed line 20 and to the right of dashed line 22, occurs when nodevice asserts either SEL or BSY. Once the BUS FREE phase of the SCSIprotocol occurs, under the ANSI standard any device connected to the busmay commence activity on the bus by moving from the BUS FREE phase tothe ARBITRATION phase, depicted between dashed line 20 and dashed line24.

[0015] As illustrated between the dashed lines 20 and 24 in FIG. 1, theARBITRATION phase of the SCSI protocol begins when one or more devicesarbitrates for the bus by simultaneously asserting BSY and its addresson the SCSI bus. The address asserted by each device during theARBITRATION phase indicates that device's priority to all other deviceson the bus. If a device's address on the DATA BUS corresponds to databit 7, then that device has the highest priority on the SCSI bus.Conversely, if a device's address on the SCSI bus corresponds to databit 0, then that device has the lowest priority on the SCSI bus.

[0016] During the ARBITRATION phase depicted between dashed lines 20 and24, each arbitrating device checks the other DATA BUS lines to determineif any higher priority device, i.e. a device that has a higher busaddress, is also concurrently arbitrating for the bus. If an arbitratingdevice detects that a higher priority device is also arbitrating, itthen ceases participating in the arbitration by negating its BSY andaddress signals. If a device ceases to arbitrate, it will not againattempt to arbitrate until the bus returns to its BUS FREE phase.Conversely, if an arbitrating device detects that its address on theDATA BUS provides it with the highest priority among the arbitratingdevices, i.e. the device won the arbitration, it then completes theARBITRATION phase by asserting SEL followed by the address of the devicewith which it wishes to communicate.

[0017] The SELECTION phase of the SCSI bus protocol, depicted betweendashed line 24 and dashed line 26 in FIG. 1, follows immediately afteran ARBITRATION phase. In the SELECTION phase, the winning device negatesI/O, asserts both its and the target's addresses on the DATA BUS andthen negates BSY which it has continuously asserted since the beginningof the ARBITRATION phase. Each device connected to the SCSI bus that iscapable of being selected recognizes that the SELECTION phase is underway and checks its address line to determine if it is being selected.The selected device responds to selection by asserting BSY. Uponreceiving the assertion of the BSY signal from the selected device, thewinning arbitrating device ends the SELECTION phase by negating SEL andthe addresses. At the end of the SELECTION phase, since the winningarbitrating device negated I/O during SELECTION it enters theinformation exchange phase(s) as the SCSI bus initiator.

[0018] Alternatively, the RESELECTION phase of the SCSI bus protocol mayfollow immediately after an ARBITRATION phase. The RESELECTION phaseresembles the SELECTION phase except that the winning arbitrating devicealso asserts I/O along with the selected device's address. After theselected device asserts BSY, the winning arbitrating device reassertsBSY and then negates SEL and the addresses. After the winningarbitrating device negates SEL and the addresses, the selected devicenegates BSY leaving the winning arbitrating device alone asserting BSY.At the end of the RESELECTION phase, since the winning arbitratingdevice asserted I/O during RESELECTION it enters the informationexchange phase(s) as the SCSI bus target.

[0019] Under the ANSI standard, the SCSI bus protocol need not includean ARBITRATION phase. The standard for the SCSI bus permits systems inwhich a sole initiating device connected to the bus moves directly fromthe BUS FREE phase to the SELECTION phase without ever entering theARBITRATION phase. However, in the more sophisticated implementations ofthe SCSI bus allowed under the ANSI standard, devices move from the BUSFREE phase to the ARBITRATION phase before entering either the SELECTIONor RESELECTION phase.

[0020] After the SELECTION phase of the SCSI bus protocol ends, theinformation exchange phases begin with the bus coming under the controlof the target device. In the example depicted in FIG. 1, the targetdevice initiates a COMMAND phase between dashed line 26 and dashed line28. This COMMAND phase is followed by a DATA phase with the data beingtransferred from the target to the initiator between dashed line 28 anddashed line 32 in FIG. 1. The DATA phase may be followed by a STATUSphase as illustrated in FIG. 1 between dashed line 32 and dashed line34. Finally, the STATUS phase may be followed by a MESSAGE phase withthe message being transferred from the target to the initiator betweendashed line 34 and dashed line 22. The SCSI standard does notestablished any order or number of phases associated with an informationexchange. Accordingly, as many COMMAND, DATA, STATUS and/or MESSAGEphases may occur as are needed to perform the desired operation. Whenthe target device completes the desired operation and is finished withthe bus, it ends the information exchange phases by negating the signalthat it is applying to the BSY signal line as illustrated at dashed line22 in FIG. 1. Negation of the signal on the BSY signal line by thetarget device returns the bus once again to the BUSS FREE phase.

[0021] For economic and other reasons, it frequently is desirable toshare a peripheral device such as a tape drive or a disk drive among anumber of computer systems without physically altering the cableconnections to those systems, and without disturbing the operation ofthose systems. Accordingly, for many years various manufacturers havesold devices that allow a computer system operator to electronicallyswitch a shared peripheral device from one computer system to another.Perhaps this practice of sharing a single peripheral device amongseveral computer systems occurs most frequently in the instance of tapedrives used for backing-up onto magnetic tape the data which is storedon disk drives.

[0022] While, conceptually, an electronic switch used to share aperipheral device among two or more computer systems does not seem verycomplicated, usually it is not so simple as a large, passive multi-polemechanical switch that connects to the buses of each of the sharingcomputer systems and to the shared peripheral device. Such a large,passive multi-pole mechanical switch is usually incompatible with theelectrical characteristics of high data transfer rate buses that connectperipheral devices to a computer system. This electrical incompatibilityoccurs because of the simultaneous presence of high frequency signals onall of the signal lines in the buses connected to the switch and becauseof the isolation required between the signals on all those buses. Evenin its simplest form, an electronic switch for selectively connecting asingle peripheral device such as a tape drive or a disk drive to one ofthe buses of several computer systems is an active electronic devicethat provides proper electrical termination for signal lines in theseveral buses while isolating all the signal lines in those buses fromeach other except for the signal lines in the pair of buses betweenwhich signals are to be exchanged.

[0023] Thus far, bus switches for arbitration type buses exist only formulti-master centralized arbitration buses. In such central arbitration,requests for access to the bus come to a single arbitration circuit.These requests to the arbitration circuit may be presented on severaldifferent bus request signal lines that respectively correspond todifferent priority levels for the requesting devices. Multiple devicesmay be connected to the same wire-OR bus request signal line. When suchbus request signals arrive at the central arbitration circuit, itdecides when and to which priority level it will grant control of thebus. The result of the arbitration circuit's decision is thentransmitted back to the devices via bus grant signal lines included inthe bus. In these central arbitration buses, the bus grant signal linesare often daisy-chained through the devices connected to the bus so thefirst requesting device at a particular priority level can blockretransmission of the grant signal to devices further along the bus fromthe central arbitration circuit and thereby take control of the bus.This daisy-chaining and grant blocking, if present, is sometimesdescribed a positional priority system.

[0024] With these central arbitration buses, since the bus requestsignals flow to the central arbitration circuit and the bus grantsignals flow from that circuit, it is relatively straight forward tobuild a bus switch that passes them between one of several sharing busesand the shared bus. By sensing whether the bus request signal and thebus grant signal pass through the switch, it can determine the properdirection to drive the bus control lines. Moreover, by sensing which ofthe two interconnected buses produces the data strobe signal and whethera read or write is occurring, the bus switch can decide in whichdirection to drive the data lines.

[0025] Conversely, in a distributed arbitration digital data bus such asthe SCSI bus, there is no central arbitration circuit. Instead, alldevices are connected to the SCSI bus in parallel. Accordingly, thereare no unidirectional request and grant lines from which the bus switchcan sense the direction of signal transmission. Instead, the digitalcomputing devices simultaneously contending for access to the SCSI busdecide among themselves which one is to receive access. The winningdevice of this arbitration then selects the device with which it willexchange data. Thus, a bus switch for the SCSI bus must appear to passall of the bus signals freely in both directions as though it were acontinuous cable while secretly determining the direction in whichsignals are truly passing. Furthermore, the bus switch's circuits mustperform this bidirectional signal transfer imperceptibly and withoutintroducing electrical disturbances (glitches) on the signal lines. Onlywith this type of signal transmission will devices on both sides of thebus switch that are competing for access to the bus be unaffected by theswitch's presence between them. If the electronic circuits included inthe switch are incapable of operating in this manner, signaling errorsmay occur.

[0026] For some interval of time, a firm named Rancho Technology hasoffered a SCSI bus repeater that interfaces between a single-ended SCSIbus and a differential SCSI bus. For each of the eighteen signal linesin a single-ended SCSI bus (or equivalently, for each of the eighteenpairs of signal lines in a differential SCSI bus), the Rancho Technologyrepeater appears to include a pair of two input NOR gates havingresistors that respectively cross-couple the output signal from each ofthe NOR gates to an input of the other NOR gate. For each of theeighteen pairs of NOR gates, this device also appears to includecapacitors connected between circuit ground and the junction between theresistors and the input of each NOR gate. In addition to the resistorsand capacitors connected to one input of the NOR gates, the second inputof one NOR gate in each of the eighteen pairs ppears to receive thesignal on one of the single-ended SCSI bus's data lines via asingle-ended receiving buffer. The second input of the other NOR gate ineach of the eighteen pairs appears to receive a single-ended outputsignal from a receiving buffer for the corresponding differential SCSIbus signal. The output signal from the NOR gate that receives thesingle-ended SCSI bus' signal appears to be connected to the controlinput of a transmitting buffer for the differential SCSI bus. The twooutputs from this transmitting buffer appear to be connected in parallelto the inputs of the buffer that receives the differential SCSI bussignal. The input signal to this transmitting buffer for thedifferential SCSI bus appears to be the single ended SCSI bus signalthat is applied to the NOR gate whose output signal appears to controlthe buffer's operation. The output signal from the other NOR gate thatreceives one of its input signals from the differential SCSI bus isapplied through a NAND gate to the single-ended SCSI bus signal line andthereby is also applied to the input of the single-ended bus' receivingbuffer.

[0027] The NOR gates in the circuit described above for the RanchoTechnology single-ended SCSI bus to differential SCSI bus repeaterappear to operate as an arbitration-latch that gives control of each ofthe SCSI bus' eighteen signal lines to the individual line in each buswhich first asserts the signal on that line. If the circuit operates inthis way, then the combined resistors and capacitors connected to theinputs of the eighteen pairs of NOR gates appear to delay latching ofthe cross-coupled NOR gates for a brief interval after assertion of thatsignal on either the single-ended or differential SCSI bus. However, thecircuit for each of the eighteen SCSI bus signal lines in the RanchoTechnology repeater appears to be asymmetric by its inclusion of a diodeconnected in parallel with one of the cross-coupling resistors. Thisdiode has its anode connected to the output of the NOR gate thatreceives the single-ended SCSI bus' signal and its cathode connected tothe junction of the resistor and capacitor connected to the input of theNOR gate which receives the signal from the differential SCSI bus. Ifthe arbitration-latch in the Rancho Technology repeater operates asdescribed above, then this diode biases the arbitration-latch'soperation to provide faster response to assertion of a SCSI bus signalon the single-ended bus than assertion of that same signal on thedifferential bus.

[0028] Reports regarding the operation of the Rancho Technology SCSI busrepeater indicate that its eighteen relatively simple circuits, all ofwhich operate independently of each other (e.g. there is no coupling ofsignal state on the SCSI bus' BSY signal line to its SEL, DB0-DB7, orDBP signal lines), does not operate reliably under all circumstances. Itappears that for some SCSI bus applications the Rancho Technologysingle-ended to differential SCSI bus repeater operates satisfactorilyand for other applications it operates unsatisfactorily. It appearsreasonable to infer that the inconsistent operation of the RanchoTechnology SCSI bus repeater is in some unknown way due to thesimpleness of its circuit when that circuit is required to respond tosignals from SCSI bus devices that employ sophisticated features of theSCSI bus protocol, e.g. reselection. It further appears that thisrepeater may have been designed to operate properly in SCSI systems inwhich arbitrating devices connect only to the single-ended bus.

DISCLOSURE OF INVENTION

[0029] An object of the present invention is to provide arepeater/switch for interconnecting two of two or more distributedarbitration digital data buses.

[0030] Another object of the present invention is to provide arepeater/switch for interconnecting two of two or more bidirectionaldigital data buses having signal lines that may, at some instant intime, be either driven or received by any device on the bus.

[0031] Another object of the present invention is to provide arepeater/switch for interconnecting two of two or more bidirectionaldigital data buses in which no signal present on the buses can be reliedupon to always be driven in a particular direction through any point onthe bus between any two devices.

[0032] Another object of the present invention is to provide arepeater/switch for interconnecting two of two or more bidirectionaldigital data buses in which the signal present on no signal line may berelied upon to determine whether another signal line in the bus is beingdriven or not by a particular device on the bus.

[0033] Another object of the present invention is to provide a switchfor sharing a device among one of several distributed arbitrationdigital data buses, such as those operating in accordance with the SCSIstandard, without physically disconnecting the conductors over whichthose buses transmit their respective signals.

[0034] Another object of the present invention is to provide a busrepeating/switching device that is easily and economically adapted toalternative electrical standards for signal transmission over one ormore of several buses.

[0035] Another object of the present invention is to provide a busrepeating/switching device that facilitates requesting access to ashared bus.

[0036] Another object of the present invention is to provide a busrepeater/switch that indicates when devices having both single-ended anddifferential bus interface circuits are simultaneously connected to thesame SCSI bus.

[0037] Yet another object of the present invention is to provide a busrepeater/switch that is cost effective, simple to manufacture, easy tomaintain, and economical to manufacture.

[0038] Briefly, the present invention is a bus repeater/switch forelectronically exchanging digital control and data signals between aselected one of several sharing distributed arbitration buses and ashared distributed arbitration bus. In the embodiment of the inventiondisclosed herein, the distributed arbitration buses conform to the ANSIstandard for the SCSI bus. The repeater/bus switch includes a pluralityof bus interface cards, equal in number to the number of buses, thatconnect to the distributed arbitration buses for receiving signals fromand transmitting signals to devices connected thereto. The bus interfacecards connect to a control card that allows signals from one of thesharing buses to be exchanged with the shared bus via the control cardand the interface cards respectively connected to the selected sharingbus and to the shared bus. The bus switch also includes a selectorswitch for choosing which particular one of the sharing buses exchangesdigital data signals with the shared bus. In the preferred embodiment,the selector switch means includes a plurality of switches equal innumber to the plurality of the sharing bus interface cards. Each ofthese switches is associated with a sharing bus interface card and withthe sharing bus connected thereto. Activation of a switch generates aselection signal that requests exchanging of control and data signalsbetween the shared bus and the sharing bus with which the switch isassociated.

[0039] The repeater or bus switch responds to signals on the distributedarbitration buses and to phases of the protocol for those signals sothat its presence between pairs of buses is imperceptible to devicesconnected thereto. In the particular embodiment disclosed herein, therepeater/bus switch responds to the ARBITRATION and SELECTION phases ofthe SCSI bus protocol to prevent the creation of glitches in the signalsthat it applies to the buses and to prevent the propagation of glitchesbetween interconnected pairs of buses.

[0040] These and other features, objects and advantages will beunderstood or apparent to those of ordinary skill in the art from thefollowing detailed description of the preferred embodiment asillustrated in the various drawing figures.

BRIEF DESCRIPTION OF DRAWINGS

[0041]FIG. 1 is a pulse timing diagram depicting signals present on thevarious lines of the SCSI bus during a sequence of phases in the bus'operation;

[0042]FIG. 2 is a block diagram depicting digital data buses 35interconnecting a network of computing devices, including a bus switchin accordance with the preferred embodiment of the invention having acontrol card and a plurality of interface cards;

[0043]FIG. 3 is a block diagram depicting a network of computingdevices, similar to that depicted in FIG. 2, that illustrates analternative embodiment of the bus switch;

[0044]FIG. 4, assembled by combining FIGS. 4a and 4 b, is a block/logicdiagram depicting a single-ended interface card for the bus switch ofFIGS. 2 and 3 including the interface card's Programmable-Array Logic(“PAL”);

[0045]FIG. 5 is a block/logic diagram, drawn at one-half the scale ofFIG. 4, depicting the control card of the bus switch of FIGS. 2 and 3including the control card's bus switch state sequencer;

[0046]FIG. 6, assembled by combining FIGS. 6a and 6 b is a logic diagramdepicting the control card's bus switch state sequencer; and

[0047]FIG. 7 is a logic diagram depicting the interface card's PAL.

BEST MODE FOR CARRYING OUT THE INVENTION

[0048]FIG. 2 depicts a network of computing devices including a busswitch 40 in accordance with the present invention enclosed within adashed line. The bus switch 40 includes a printed circuit control card44 having a single shared bus interface connector 46 a and a pluralityof sharing bus interface connectors 46 b that respectively receive andelectrically connect to printed circuit interface cards 48. In additionto electrically connecting to the control card 44 through the interfaceconnectors 46 a or 46 b, each of the interface cards 48 is alsoelectrically connected to one of several sharing data buses 52, 54 or56, or to a shared data bus 58 through a SCSI bus connector 60. Alsoconnected to the data buses 52, 54, 56 or 58, in addition to the busswitch 40, are other devices such as digital computers 62, a tape drive64, and various different types of disk drives such as floppy diskdrives 66, hard disk drives 68, a Compact Disk Read Only Memory (“CDROM”) drive 72, and a Write Once Read Many (“WORM”) drive 74.

[0049] In the preferred embodiment of the present invention, all thedata buses 52, 54, 56 and 58 conform to the ANSI standard for the SCSIbus. While only three sharing buses 52, 54, and 56 are illustrated inFIG. 1, in principle there is no limit on the number of interface cards48 that may be included in the bus switch 40. Accordingly, the busswitch 40 may be constructed to allow selectively connecting the shareddata bus 58 with any one of an unlimited number of sharing data busesincluding the sharing data buses 52, 54 and 56 such as are depicted inFIG. 2.

[0050] In accordance with the SCSI bus standard only single-ended oronly differential SCSI bus devices may be connected to each of the databuses 52, 54, 56 and 58. However, as will be explained in greater detailbelow, all of the data buses 52, 54, 56 and 58 need not be exclusivelysingle-ended or exclusively differential. For example, all of thedevices connected to the sharing data buses 52 and 56 might besingle-ended while all of the devices connected to the sharing data bus54 and the shared data bus 58 might be differential. Thus, in additionto providing a switch for the SCSI bus, the bus switch 40 may alsofunction as an adapter that allows data to be exchanged betweensingle-ended and differential SCSI buses.

[0051] In the preferred embodiment, included in the bus switch 40 andassociated with each of the computers 62 is a shared bus-request box 76.Each shared bus-request box 76 connects through a shared bus-requestcable 78 and a shared bus-request connector 82 to one of the interfacecards 48. Each of the shared bus-request cables 78 is associated withone of the sharing data buses 52, 54 or 56 and each of the sharedbus-request boxes 76, which preferably is mechanically secured to thecomputer 62 by a piece of Velcro®, is also associated with that samesharing data bus 52, 54 or 56. Each of the shared bus-request boxes 76includes a toggle switch 84 and a Light Emitting Diode (“LED”) 86.

[0052] By closing the contacts of the toggle switch 84 in the sharedbus-request box 76 attached to a particular computer 62, an operator ofthe computer 62 transmits a signal to the interface card 48 to which thetoggle switch 84 is connected by the shared bus-request cable 78requesting that the bus switch 40 connect the shared data bus 58 withthe particular sharing data bus 52, 54 or 56 with which the toggleswitch 84 is associated. To free the shared data bus 58 for connectionwith other sharing data buses 52, 54 or 56, the operator opens thecontacts of the toggle switch 84 thereby terminating the request signal.

[0053] After closure of the contacts of one of the toggle switches 84requests connection of one of the sharing data buses 52, 54 or 56 withthe shared data bus 58, and the shared data bus 58 and the sharing databus 52, 54 or 56 both enter the BUS FREE phase of SCSI bus protocol, andall other toggle switches 84 are open, the bus switch 40 connects theshared data bus 58 with the sharing data bus 52, 54 or 56 associatedwith the toggle switch 84 having closed contacts. Upon connecting theshared data bus 58 with one of the sharing data buses 52, 54, or 56, thebus switch 40 provides a visual indication that the connection has beenformed by illuminating the LED 86 in the shared bus-request box 76secured to the particular computer 62 for which interconnection has beenrequested.

[0054] As controlled by the closing of contacts on the various toggleswitches 84 and by operating conditions on the data buses 52 through 58,at any instant in time the bus switch 40 may exchange signals betweenthe shared data bus 58 and one of the sharing buses 52, 54 or 56 whilesimultaneously isolating that pair of communicating buses from theremainder of the sharing data buses 52, 54 or 56. Thus, at any instantin time the bus switch 40 electrically interconnects the shared data bus58 with any one of the sharing data buses 52, 54 or 56 to establishcomposite buses 52-58, 54-58 or 56-58 and exchanges-control and datasignals back and forth between the pair of buses that it interconnectsto form the composite bus. Accordingly, at any instant in time only oneof the LEDs 86 may be illuminated.

[0055] When the request for interconnection of the shared data bus 58with one of the sharing data buses 52, 54 or 56 is terminated by openingthe contacts of the toggle switch 84, the bus switch 40 indicates thesevering of that connection by extinguishing the LED 86 at the computer62. If, inadvertently, a request for interconnection of the shared databus 28 with one of the sharing data buses 52, 54 or 56 is maintainedwhen it is, in fact, no longer required, thereby preventinginterconnection of the shared data bus 58 with other sharing data buses52, 54 or 56, and it is physically impossible to open the contacts ofthe toggle switch 84, e.g. the shared bus-request box 76 is located in alocked office, the bus request signal may be terminated simply byunplugging the appropriate shared bus-request cable 78 from itsconnector 82.

[0056]FIG. 3 depicts a network of computing devices substantiallyidentical to that depicted in FIG. 2 that illustrates an alternativeembodiment of the bus switch. Those elements depicted in FIG. 3 that arecommon to the network of computing devices or to the bus switch 40depicted in FIG. 2 carry the same reference numeral distinguished by aprime (“′”) designation. In FIG. 3, the shared bus-request boxes 76,together with their associated toggle switches 84 and LEDs 86, and theshared bus-request cable 78 and the shared bus-request connector 82 havebeen eliminated from the bus switch 40 depicted in FIG. 2. Providing thesame function in FIG. 3 as the shared bus-request boxes 76, the toggleswitches 84 and the LEDs 86 of FIG. 2 is a single multi-pole selectorswitch 88 that is physically enclosed within the same housing as thecontrol card 44′ and the interface cards 48′.

[0057] As controlled by the position of the selector switch 88, at anyinstant in time the bus switch 40′ connects the shared data bus 58′ toone of the sharing data buses 52′ , 54′ or 56′ while simultaneouslyisolating it from the remainder of the sharing data buses 52′ , 54′ or56′ , and also simultaneously isolating each of those other buses fromeach other. Thus, depending upon the position of the selector switch 88,at any instant in time the bus switch 40′ electrically interconnects theshared data bus 58′ with any one of the sharing data buses 52′ , 54′ or56′ to establish composite buses 52′-58′ , 54′-58′ or 56′-58′ andexchanges control and data signals back and forth between the pair ofbuses which form the composite bus. In the bus switch depicted in FIG.3, the connection of the shared data bus 58′ to a particular sharingdata bus 52′, 54′, or 56′ is indicated by illuminating the appropriateone of a plurality of LED's 92 analogously to the illumination of one ofthe LED's 86 depicted in FIG. 2.

[0058] To illustrate the preferred embodiment of the invention whilesimultaneously describing in full generality the true nature and extentof the invention, as stated above, the following discussion proceedsupon the basis that the data buses 52, 54, 56 and 58 interconnecting thevarious devices 62, 64, 66, 68, 72 and 74 and the bus switch 40 operatein accordance with the ANSI standard for the SCSI bus. Accordingly, forpurposes of the following discussion at no time may any more than eightdevices be connected to any one of the composite buses 52-58, 54-58 or56-58. Furthermore, each device connected to the composite buses 52-58,54-58 and 56-58 must have a unique address on the respective compositebuses 52-58, 54-58 and 56-58 to which they are connected regardless ofthe configuration of the buses established by the operation of the busswitch 40.

[0059] Interface Card 48

[0060]FIG. 4, made up of FIG. 4a and 4 b, schematically depicts thedigital logic circuits included in a single-ended interface card 48.Interface cards of this type depicted in FIG. 4 may be connected to thecontrol card 44 at any of its interface connectors 46 a or 46 b toexchange signals between the control card 44 and any of the sharing databuses 52, 54 or 56, or with the shared data bus 58.

[0061] The signals present at the SCSI bus connector 60 depicted in FIG.4 includes a BSY control signal line 102, a SEL control signal line 104,C/D, I/O, MSG and REQ control signal lines 106 (only one of which isdepicted in FIG. 4b with the additional lines indicated only by dotswithin the SCSI bus connector 60 immediately above and below the line106), ACK and ATN control signal lines 108 (only one of which isdepicted in FIG. 4b with the additional lines indicated only by a dotwithin the SCSI bus connector 60 immediately below the line 108), a RSTcontrol signal line 110, and the eight DB0-DB7 data signal lines and oneDBP parity signal line 112 (only one of which is depicted in FIG. 4 withthe additional lines indicated only by dots within the SCSI busconnector 60 immediately above the line 112). The eight data signallines 112, DB0-DB7, and the parity signal line 112, DBP, constitute theDATA BUS portion of the SCSI bus.

[0062] The single-ended interface card 48 depicted in FIG. 4 includes aswitched transceiver circuit 122 for the BSY signal line 102, a switchedtransceiver circuit 124 for the SEL signal line 104, four switchedtransceiver circuits 126 (only one of which is illustrated in FIG. 4)respectively for the C/D, I/O, MSG and REQ signal lines 106, twoswitched transceiver circuits 128 (only one of which is illustrated inFIG. 4) respectively for the ACK and ATN signal lines 108, a switchedtransceiver circuit 130 for the RST signal line 110, and nine switchedtransceiver circuits 132 (only one of which is illustrated in FIG. 4)for the DATA BUS of the SCSI bus. Each of the switched transceivercircuits 122-132 is enclosed within a dashed line box in FIG. 4.

[0063] Though each of the switched transceiver circuits 122-132 isslightly different from all of the other switched transceiver circuits122-132, all of the transceiver circuits 136-132 include a tri-statereceiving buffer 136 and a tri-state transmitting buffer 138. Thereceiving buffer 136 and the transmitting buffer 138 of the switchedtransceiver circuits 122-132 may be 74LS125 integrated circuits. Each ofthe buffers 136 and 138 includes a control input 140 to which a logiclow signal is applied if the signal present at the input of the buffers136 and 138 is to appear at their respective outputs. Applying a logichigh signal to the control input 140 of the buffers 136 and 138 causestheir outputs to become open circuited.

[0064] Because the bus switch 40 must continuously monitor therespective states of the BSY signal line 102 and the SEL signal line 104even when the switch 40 is not exchanging signals between the shareddata bus 58 and one of the sharing data buses 52, 54, or 56 and in somonitoring the states of those signals must present only a singleelectrical load to the bus 52, 54, 56 or 58, the control input 140 ofthe receiving buffer 136 for both of the switched transceiver circuits122 and 124 is connected to circuit ground. Grounding the control inputs140 of the receiving buffers 136 in the BSY signal switched transceivercircuit 122 and the SEL signal switched transceiver circuit 124 causesthe state of the signals on the BSY signal line 102 and the SEL signalline 104 to always be present at their respective outputs. Because anoutput signal is always present at the outputs of the receiving buffers136, both the BSY signal switched transceiver circuit 122 and the SELsignal switched transceiver circuit 124 include a second tri-stateintermediate buffer 142 that respectively receives those output signals.The intermediate buffers 142 may also be 74LS125 integrated circuits.

[0065] To provide a source of termination power in accordance with theANSI standard for the SCSI bus, the interface card 48 includes a 1N4002diode 144 having an anode 146 which is connected to Vcc and a cathode148 which is connected to a TERMPWR line 152 included in the SCSI busconnector 60. If a particular interface card 48 connects at either endof the SCSI bus, then in accordance with the ANSI standard, for each ofthe signal lines in the SCSI bus, it must include pairs of seriesconnected termination resistors 154 and 156. As illustrated in FIG. 4,one end of each pair of series connected termination resistors 154 and156 is connected to the TERMPWR line 152, the other end is connected tocircuit ground, and their junction is connected to the respective signalline 102-112. If the interface card 48 is connected between the ends ofone of the SCSI buses 52-58 depicted in FIG. 1, then all of theresistors 154 and 156 are omitted from the interface card 48.

[0066] In addition to being applied as input signals to the intermediatebuffers 142, the signals from the outputs of the receiving buffers 136in the BSY and SEL switched transceiver circuits 122 and 124 are appliedas input signals to an interface card logic Programmable Array Logic(“PAL”) 162 respectively via a BSY BUF L signal line 164 and a SEL BUF Lsignal line 166. The interface card logic PAL 162 also receives anoutput signal from a series connected NAND gate 168 and NOR gate 172 viaa SW DEL L signal line 174. The NAND gate 168 and NOR gate 172 operateas a non-inverting buffer to provide delay. An input signal is appliedto both inputs of the NAND gate 172 and to inputs of monostablemultivibrators 176 and 178 via a SWITCH L signal line 182. Themonostable multivibrators 176 and 178 may be 74LS123 integratedcircuits. The output signals from the monostable multivibrators 176 and178 are applied as input signals to the interface card logic PAL 162respectively via a SW ON TMR H signal line 183 and a SW OFF TMR H signalline 184. A resistor 186 connects the SWITCH L signal line 182 to Vccwhich is also connected directly to one input of the NAND gate 168. TheNAND gate 168, the NOR gate 172 and the two monostable multivibrators176 and 178 permit the PAL logic to debounce the signal on the SWITCH Lsignal line 182.

[0067] In the preferred embodiment of the invention illustrated in FIG.2, the signal present on the SWITCH L signal line 182 is the bus requestsignal from the toggle switch 84 located in one of the sharedbus-request boxes 76. This bus request signal is received at theinterface card 48 via the shared bus-request cable 78 and the sharedbus-request socket 82. In the alternative embodiment of the inventionillustrated in FIG. 3, the signal present on the SWITCH L signal line182 comes from the selector switch 88 depicted in FIG. 3 and is receivedat the interface card 48 via an inter-interface card connector 188included in the interface card 48.

[0068] The interface card logic PAL 162 also receives an output signalfrom a 74LS125 buffer 192 via a BUS OK L signal line 193. The buffer 192receives its input signal from a DIFFSENS line 194 which for thesingle-ended interface card 48 depicted in FIG. 2 is connected to pin 25of the SCSI bus connector 60. A resistor 196 connects the DIFFSENS line194 to circuit ground to which the control input 140 of the buffer 192is also connected. Accordingly, the signal present at the input of thebuffer 192 is always applied as an input signal to the interface cardlogic PAL 162 via the BUS OK L signal line 193. The DIFFSENS line 194and the buffer 192 provide the interface card logic PAL 162 with asignal that indicates whether or not a device adapted for exchangingsignals over the SCSI bus using the differential signal convention isconnected to the single-ended interface card 48 by detecting whether asource of differential termination network power is present on a linethat is unused on the single-ended SCSI bus. If the PAL 162 of thesingle-ended interface card 48 receives a signal indicating that it isconnected to a differential type SCSI device, it immediatelyelectronically isolates the circuits on the interface card 48 from thecontrol card 44 and the bus 52, 54, 56 or 58 to which it connects.

[0069] A PRI IN L signal line 202 provides the interface card logic PAL162 with a signal from the inter-interface card connector 188. A PRI OUTL signal line 204 transmits a signal from the interface card logic PAL162 to the inter-interface card connector 188. Within the housing forthe bus switch 40 but external to the interface card 48, the PRI IN Lsignal lines 202 and the PRI OUT L signal lines 204 are “daisy-chained”from the control card 44 through all of the interface cards 48 whichconnect to the sharing data buses 52, 54 and 56. The daisy-chainedsignal on the PRI IN L signal lines 202 and the PRI OUT L signal lines204 permits the interface cards 48 to resolve contention for the shareddata bus 58 among themselves. The SWITCH L signal line 182 and PRI IN Lsignal line 202 on the shared interface card 48 are wired to ground andthus the shared interface card 48 is enabled at all times.

[0070] The interface card logic PAL 162 also provides an output signalon a BOARD SELECT L signal line 212 to an input of a NOR gate 214. Theother input of the NOR gate 214 is connected to Vcc and its output isconnected via a BOARD ENB H signal line 216 to an input of a NAND gate218. The other input of the NAND gate 218 is also connected to Vcc andits output is connected via a BOARD ENB L signal line 222 to a controlinput 140 of a 74LS125 buffer 224. The input to the buffer 224 isconnected to circuit ground while its output signal is transmitted viaresistors 226 and 228 respectively to the shared bus-request connector82 and the inter-interface card connector 188. The output signal fromthe buffer 224 passes through the resistor 226 through the sharedbus-request connector 82 and the shared bus-request cable 78 to the LED86 included in the shared bus-request box 76. Analogously, in thepreferred embodiment of the present invention the output signal from thebuffer 224 passes through the resistor 228 through the inter-interfacecard connector 188 and a cable located within the housing of the busswitch 40 to an LED, such as one of the LEDs 92 illustrated in FIG. 3.This LED, which is not illustrated in FIG. 2, is preferably located onthe housing for the bus switch 40 adjacent to the SCSI bus connector 60and shared bus-request connector 82 to be visible from the outside ofthe housing. Thus, the LED connected to the resistor 228 of theinterface card 48 provides a visual indication at the bus switch 40 ofwhich of the sharing data buses 52-56 is enabled to exchange signalswith the shared data bus 58.

[0071] A low signal present on the BOARD SEL L signal line 212 producesa high signal present on the BOARD ENB H signal line 216 and a low onthe BOARD ENB L signal line 222 to enable the interface card 48 forexchanging signals between the shared data bus 52, 54 or 56 to which itis connected and the control card 44. Only one of the interface cards 48connected to the shared data buses 52, 54 or 56 may be enabled at anytime. Enabling an interface card 48 does not necessarily mean that datais actually being transferred from the sharing data bus 52, 54 or 56 tothe shared data bus 58 via the enabled interface card 48. Rather itmerely means that the bus switch 40 is enabled to respond to thesignaling protocol on the SCSI bus for exchanging signals between theshared data bus 58 and the sharing data bus 52, 54 or 56 that isconnected to the enabled interface card 48. Data exchanges between thatparticular sharing data bus 52, 54 or 56 and the shared data bus 58occur only as part of a sequence of phases occurring on the SCSI bussuch as those illustrated in FIG. 1. The fact that a particular sharingdata bus 52, 54 or 56 is enabled for such data exchanges is indicatedboth at the housing for the bus switch 40 and in the preferredembodiment at the shared bus-request box 76 by illumination of theirrespective LEDs.

[0072] In addition to enabling the buffer 224 for illuminating the LEDs86 and 92, the signal on the BOARD ENB L signal line 222 is alsosupplied to the control inputs 140 of the intermediate buffers 142 inthe switched transceiver circuits 122 and 124 respectively for the BSYand SEL signals, and to the control inputs 140 of the receiving buffers136 in the switched transceiver circuit 130 for the RST signal and nineswitched transceiver circuits 132 for the DATA BUS portion of the SCSIbus. Thus, whenever the BOARD ENB L signal of the interface card 48 isasserted, the series connected buffers 136 and 142 in each of theswitched transceiver circuits 122 and 124, and the buffers 136 in theswitched transceiver circuit 130 and the nine switched transceivercircuits 132 respectively transmit the BSY, SEL, RST and DATA BUSsignals from the SCSI bus connector 60 to the interface connector 46.Accordingly, when the BOARD ENB L signal is asserted, the signal on theBSY control signal line 102 of the SCSI bus is supplied to the controlcard 44 via a BSY IN L signal line 232. In a similar way, the controlcard 44 receives the signals present on the SEL control signal line 104via a SEL IN L signal line 234, on the RST control signal line 110 via aRST IN L signal line 236, and on the eight data signal lines, DB0-DB7,and one parity signal line, DBP, 112 via nine DBn IN L signal lines 238.(Note that FIG. 4 depicts only one of the eight data signal lines 112while dots in the connector 46 indicated the presence of the other 8signal lines.) The BSY, SEL and DB0-DB7 and DBP signals are alwayssupplied to the control card 44 when the interface card 44 is enabledbecause the bus switch 40 must respond to signals on those lines duringthe SCSI bus' arbitration phase. Analogously, the RST signal must alsobe supplied continuously to the control card 44 because a reset signalmay occur at any time on the composite bus made up of the shared databus 58 and one of the sharing data buses 52-56.

[0073] As described above, the signal present on the BOARD ENB L signalline 222 is applied directly to the control input 140 of theintermediate buffer 142 in the switched transceiver circuits 122 and 124and to the receiving buffer 136 in the switched transceiver circuits 130and 132. Conversely, the signal present on the BOARD ENB H signal line216 is not applied directly to the control input 140 of any of thebuffers 136 or 138. Rather, the signal on the BOARD ENB H signal line216 is applied to the control inputs 140 of each of the transmittingbuffers 138 in all of the switched transceiver circuits 122-132 throughNAND gates 246. Similarly, the signal on the BOARD ENB H signal line 216is applied through NAND gates 248 to the control inputs 140 of thereceiving buffers 136 in the switched transceiver circuits 126 and 128.Though not expressly so depicted in FIG. 4, in all four switchedtransceiver circuits 126 for the SCSI bus' C/D, I/O, MSG and REQ signalsof the preferred embodiment, the control inputs 140 of the fourreceiving buffers 136 connect to the output of a single NAND gate 248 toreduce the number of logic gates. Similarly, for both switchedtransceiver circuits 128 for the SCSI bus' ACK and ATN signals, thecontrol inputs 140 of the receiving buffers 136 connect to the output ofa single NAND gate 248. Analogously, for all four switched transceivercircuits 126 for the SCSI bus' C/D, I/O, MSG and REQ signals, thecontrol inputs 140 of the transmitting buffers 138 connect to the outputof a single NAND gate 246. Correspondingly, for both switchedtransceiver circuits 128 for the SCSI bus' ACK and ATN signals, thecontrol input 140 of the transmitting buffers 138 connect to the outputsignal of a single NAND gate 246.

[0074] Due to the use of these single NAND gates 246 and 248, at alltimes all four C/D, I/O, MSG and REQ switched transceiver circuits 126on the interface card 48 operate in unison transmitting to or receivingsignals from the SCSI bus. Similarly, both the switched transceivercircuits 128 for the ACK and ATN signals also operate in unison. Thus,when activated, the four of the switched transceiver circuits 126included in the interface card 48 either transmit the C/D, I/O, MSG orREQ signals from one of the SCSI buses 52-58 to the control card 44respectively via a C/D IO L, I/O IO L, MSG IO L or REQ IO L controlsignal lines 242, or transmit signals on those lines from the controlcard 44 to one of the SCSI bus 52-58. Similarly, when activated, both ofthe switched transceiver circuits 128 either transmit the ACK and ATNsignals from one of the SCSI buses 52-58 to the control card 44respectively via an ACK IO L or ATN IO L control signal lines 244, orconversely. (Note that FIG. 4 expressly depicts only one of each of thesignal lines 242 and 244. However, dots in the connector 46 indicate theremaining three signal lines 242 and the additional signal line 244.)

[0075] In addition to the signal present on the BOARD ENB H signal line216, each of the NAND gates 246 and 248 receives a control signal fromthe control card 44. Thus, the NAND gate 246 of the switched transceivercircuit 122 receives a BSY ENB H control signal via a BSY ENB H signalline 252, the NAND gate 246 of the switched transceiver circuit 124receives a SEL ENB H control signal via a SEL ENB H signal line 254, thesingle NAND gate 246 for all four switched transceiver circuits 126receives a CTL OUT H control signal via a CTL OUT H signal line 256, thesingle NAND gate 246 for both switched transceiver circuits 128 receivesa RPLY OUT H control signal via a RPLY OUT H signal line 258, the NANDgate 246 of the switched transceiver circuit 130 receives a RST ENB Hcontrol signal via a RST ENB H signal line 260, and the NAND gates 246in each of the nine switched transceiver circuits 132 receives a DBn ENBH control signal via a DBn ENB H signal line 262. Analogously, thesingle NAND gate 248 for all four switched transceiver circuits 126receives a CTL IN H control signal via a CTL IN H signal line 264, andthe single NAND gate 248 for both of the switched transceiver circuits128 receives a RPLY IN H control signal via a RPLY IN H signal line 266.

[0076] In addition to transmitting the BOARD SELECT L signal via theBOARD SELECT L signal line 212 to control the operation of the switchedbuffer circuits 122-132 included in the interface card 48, the PAL 162directly transmits, from the interface card 48 to the control card 44,both a CHANGE REQUESTED L signal via a CHANGE REQUESTED L signal line272, and a BUS CONNECTED L signal via a BUS CONNECTED L signal line 274.The PAL 162 also receives both a BUS IDLE L signal via a BUS IDLE Lsignal line 276 and a DC OK L signal via a DC OK L signal line 278directly from the control card 44. The circuit ground of the controlcard 44 is supplied to the interface card 48 via a GND line 282 thatconnects directly to the input of the transmitting buffer 138 of theswitched transceiver circuit 122. Similarly, the transmitting buffer 138included in the switched transceiver circuit 124 receives a signal fromthe control card 44 via a SEL OUT L signal line 284, and the buffer 138included in each of the nine switched transceiver circuits 132 receivesa signal from the control card 44 via a DBn OUT L signal line 286.

[0077] Control Card 44

[0078] Referring now to FIG. 5, depicted there is a block diagram of thecontrol card 44. Note, that while for pedagogical reasons FIGS. 2 and 3depict the control card 44 as including a plurality of sharing businterface connectors 46 b, the preferred embodiment of the invention hasonly a single connector on the control card 44 as depicted in FIG. 5. Tocarry signals between the control card 44 and the sharing interfacecards 48, a multi-connector ribbon cable connects to the control card 44and connects in parallel to each of the sharing interface cards 48. Forthe signal lines of FIG. 5 that pass directly across the control card 44between the same signal lines on both the shared bus interface connector46 a and the sharing bus interface connector 46 b, the reference numbersin FIG. 5 are identical to those set forth in FIG. 4. For those signallines that do not pass through the control card 44 between theconnectors 46 a and 46 b, the reference numbers in FIG. 5 are the sameas those in FIG. 4 with either the letter “a” or “b” appended to thereference number to correspond with the connector 46 a or 46 b to whichthe signal line connects. Finally, for those signal lines that passacross the control card 44 between different signal lines of theconnectors 46 a and 46 b, the text below expressly sets forth thereference number designations.

[0079] As depicted in FIG. 5, the control card 44 includes a bus switchstate sequencer 302 that exchanges signals with the PAL 162 included ineach of the interface cards 48 via the signal lines 272-278. Note,however, that for the shared bus interface card 48 connected to theshared bus interface connector 46 a, its output signals CHANGE REQUESTEDL on line 272 a and BUS CONNECTED L Dn line 274 a are not used but aremerely connected to Vcc via resistors 304 and 306 to facilitate testing.

[0080] The control card 44 includes an arbitration-latch that functionsas a two-way, first-come first-served contention resolver for the SCSIbus' SEL signals received from the shared interface card 48 and from theenabled sharing interface card 48. The arbitration-latch includes two,three-input NAND gates 312 and 314. One input of each of the NAND gates312 and 314 is cross-coupled to the output of the other gate 314 and 312by the SEL ENB H signal lines 254 a and 254 b respectively from theshared bus interface connector 46 a and the sharing bus interfaceconnectors 46 b. Another input to both NAND gates 312 and 314 is thesignal present on the BUS CONNECTED L signal line 274 b. Thus, when thesignal on the BUS CONNECTED L signal line 274 b is asserted, i.e. whenone of the sharing bus interface cards 48 is enabled, thearbitration-latch formed by the NAND gates 312 and 314 may be set to onestate or the other by the signal applied respectively to their thirdinputs.

[0081] The third input of the NAND gate 312 connects to a SEL IN L toSEL B OUT L signal line 316. In addition to connecting to an input ofthe NAND gate 312, the signal line 316 directly connects the SEL IN Lsignal line 234 of the shared bus interface card 48 with the SEL OUT Lsignal lines 284 of all sharing bus interface cards 48 respectivelyconnected to the several sharing bus interface connectors 46 b.Similarly, a SEL A OUT L to SEL B IN L signal line 318 connects to aninput of the NAND gate 314 and directly connects the SEL OUT L signalline 284 of the shared bus interface card 48 with the SEL IN L signalline 234 of all sharing bus interface cards 48. The signal line 316allows the signal present on the SEL signal lines of the shared data bus58 to pass directly through the shared bus interface card 48 and thecontrol card 44 to the input of the transmitting buffer 138 of theswitched transceiver circuit 124 of all the sharing bus interface cards48. Similarly, the signal line 318 allows the signal present of the SELsignal line of the sharing data bus 52, 54 or 56 connected to theenabled interface card 48 to pass directly through the card 48 and thecontrol card 44 to the input of the transmitting buffer 138 of theswitched transceiver circuit 124 of the shared bus interface card 48.

[0082] Assuming that the signal present on the BUS CONNECTED L signalline 274 b is asserted, the circuit made up of the switched transceivercircuits 124 both in the shared bus interface card 48 and in enabledsharing bus interface card 48 together with the two NAND gates 312 and314 functions as a bidirectional repeater for SEL signals on the SCSIbus in the following manner. While both of the SCSI bus' SEL signallines are negated, both sides of the arbitration-latch formed by theNAND gates 312 and 314 are forced to be negated (low). Negation of theoutput signals from both NAND gates 312 and 314 disables thetransmitting buffer 138 in the switched transceiver circuits 124 of allinterface cards 48. In this state the inputs to NAND gates 312 and 314receive the SEL signals from the SCSI buses respectively via SEL A IN Lto SEL B OUT L signal line 316 and the SEL A OUT L to SEL B IN L signalline 318. When some device connected to either the shared data bus 58 orto the enabled sharing data bus 52, 54 or 56 asserts its SEL signal bydriving it low, that signal passes through the switched transceivercircuit 124 on the interface card 48 receiving the asserted SEL signalto the input of one of the NAND gates 312 or 314. Application of theasserted SEL signal to the input of the NAND gates 312 or 314 causesthat gate's output signal to be asserted (high). The asserted outputsignal from either NAND gate 312 or 314 blocks the other NAND gate 314or 312 from responding to assertion of the SEL signal on the other SCSIbus. In addition, assertion of the output signal from the NAND gate 312or 314 enables the transmitting buffer 138 in the switched transceivercircuit 124, on the interface card 48 that did not first receive theasserted SEL signal, to transmit that signal onto the other SCSI bus.Note that the assertion of the SEL signal on one SCSI bus reaches theother SCSI bus after a brief interval due to the circuit delay of theNAND gate 312 or 314, and the delays of the NAND gate 246 and theenabling of the transmitting buffer 138 in the switched transceivercircuit 124 that transmits the SEL signal. However, subsequent negationof the SEL signal on the first SCSI bus reaches the second SCSI buswithout those delays because the transmitting buffer 138 in the switchedtransceiver circuit 124 is already enabled. Furthermore, negation of theSEL signal on the second SCSI bus by the transmitting buffer 138 will beremoved from that bus a brief interval after the signal reaches theinput of the buffer 138 because the buffer 138 is enabled when thenegation signal first arrives at its input and is disabled shortlythereafter when the negation signal completes propagating through one ofthe NAND gates 312 or 314, one of the NAND gates 246, and the controlinput 140 of the switched transceiver circuit 138. Consequently,negation of the SEL signal on the first SCSI bus causes the SEL signalon the second SCSI bus to first be driven toward or even to the negatedstate, and then lets the line float free to be negated by thetermination resistors 154 and 156 after the transmitting buffer 138 isdisabled.

[0083] For reasons to be described in greater detail below, it isimportant to note at this juncture that signals passing throughbidirectional repeaters made up of the switched transceiver circuits 124for the SCSI bus' SEL signal both in the shared bus interface card 48and in enabled sharing bus interface card 48 together with the two NANDgates 312 and 314 of the arbitration-latch on the control card 44 aredelayed longer for transitions from the negated to the asserted statethan for transitions from the asserted to the negated state. Thus, thesebidirectional repeaters shorten the width of pulses that go from thenegated state to the asserted state and then back to the negated state.However, because active handshaking between SCSI bus devices coordinatesthe ARBITRATION and SELECTION or RESELECTION phases of the SCSI bus'sprotocol during which these bidirectional repeaters operate, the pulsewidth shortening that they introduced does not adversely effect SCSI busoperation. Moreover, this pulse shortening prevents circuit malfunctionsuch as oscillation.

[0084] Because SCSI bus devices may skip the ARBITRATION phase of theSCSI protocol and directly enter the protocol's SELECTION phase, thebidirectional repeater for the SCSI bus' SEL signal described aboveillustrates the simplest of all the bidirectional repeaters included inthe bus switch 40. To accommodate the requirements of SCSI bus signalsother than its SEL signal, the bus switch 40 includes other, morecomplicated bidirectional repeaters whose operation may now be moreeasily understood with reference to the bidirectional repeater for theSEL signal.

[0085] In addition to the bidirectional repeater for the SCSI bus' SELsignal, the control card 44 also includes nine identical bidirectionalrepeaters for the SCSI bus' DB0-DB7 and DBP signals only one of which isdepicted in FIG. 5. Similar to the bidirectional repeater for the SELsignal, the bidirectional repeaters for the SCSI bus' DB0-DB7 and DBPsignals includes an arbitration-latch that has two, three-input ANDgates 322 and 324. Each of the AND gates 322 and 324 supplies its outputsignal respectively to an input of one of two NOR gates 326 and 328.Similar to the arbitration-latch for the SEL signal, the NOR gates 326and 328 apply their respective output signals via the DBn ENB H signallines 262 a and 262 b to inputs of the AND gates 324 and 322. Since theNOR gates 328 and 326 respectively receive the output signal from theAND gates 324 and 322, the output signals from the AND gates 322 and 324are effectively cross-coupled in a manner similar to the cross-couplingof the NAND gates 312 and 314 described above. Similar to thearbitration-latch for the SEL signal, another input to both AND gates322 and 324 is the signal present on the BUS CONNECTED L signal line 274b. Consequently, when the signal on the BUS CONNECTED L signal line 274b is asserted, the arbitration-latch formed by the AND gates 322 and 324and the NOR gates 326 and 328 may be set to one state or the other bythe signals applied respectively to the third inputs of the AND gates322 and 324.

[0086] The third input of the AND gate 322 connects to a DBn A IN L toDBn B OUT L signal line 332. In addition to connecting to an input ofthe AND gate 322, the signal line 332 directly connects the DBn IN Lsignal line 238 of the shared bus interface card 48 with the DBn OUT Lsignal lines 286 of all sharing bus interface cards 48 connected to theseveral sharing bus interface connectors 46 b. Similarly, a DBn A OUT Lto DBn B IN L signal line 334 connects to an input of the AND gate 324and directly connects the DBn OUT L signal line 286 of the shared businterface card 48 with the DBn IN L signal line 238 of all sharing businterface cards 48. The signal lines 332 in each of the nine circuitsincluded in the control card 44 respectively allow the signal present onone of the DB0-DB7 or DBP signal lines of the shared data bus 58 to passdirectly through the shared bus interface card 48 and the control card44 to the input of the transmitting buffer 138 of the correspondingswitched transceiver circuit 132 of all the sharing bus interface cards48. Similarly, the signal lines 334 in each of the nine circuitsincluded in the control card 44 respectively allow the signal present onone of the DB0-DB7 or DBP signal lines of the sharing data bus 52, 54 or56 connected to the enabled interface card 48 to pass directly throughthe card 48 and the control card 44 to the input of the transmittingbuffer 138 of the switched transceiver circuit 132 of the shared businterface card 48.

[0087] During the ARBITRATION and SELECTION phases of the SCSI busprotocol, each of the nine identical bidirectional repeaters for theSCSI bus' DB0-DB7 and DBP signals operates similarly to that describedabove for the SCSI bus' SEL signal bidirectional repeater. Consequently,during the ARBITRATION and SELECTION phases of the SCSI bus protocolthese nine bidirectional repeaters shorten the width of pulses that gofrom the negated state to the asserted state and then back to thenegated state on the DB0-DB7 and DBP signal lines making up the DATA BUSportion of the SCSI bus. However, during the information phases of theSCSI bus protocol, especially during high-speed synchronous dataexchanges over the SCSI bus, changing pulse width must be avoided.Accordingly, to prevent changing pulse widths during the informationphases of the SCSI bus protocol, the bus switch state sequencer 302supplies signals to an input of one of the NOR gates 326 or 328respectively via a DATA A TO B L signal line 336 b or a DATA B TO A Lsignal line 336 a to override the operation of the arbitration-latch.Overriding the arbitration-latch signals with a signal supplied oneither of the lines 336 a or 336 b by the bus switch state sequencer 302enables one or the other of the transmitting buffers 138 in all nineswitched transceiver circuits 132. Enabling one or the othertransmitting buffers 138 in all nine switched transceiver circuits 132forces DB0-DB7 and DBP signal transfers to occur in one direction or theother between the shared data bus 58 and the sharing data bus 52, 54 or56 connected to the enabled interface card 48. Continuously enabling thetransmitting buffers 138 in this way irrespective of the actual state ofsignals present on the DB0-DB7 and DBP signal lines prevents changingthe width of pulses on the SCSI buses' DB0-DB7 and DBP signal lines.

[0088] The control card 44 also includes a third different type ofbidirectional repeater for the RST signals of the two SCSI buses.Similar to the other bidirectional repeaters, the bidirectional repeaterfor the RST signals includes an arbitration-latch that has two AND gates342 and 344. As depicted in FIG. 5, the AND gate 342 receives four inputsignals while the AND gate 344 receives only three. The AND gate 344supplies its output signal to an input of an OR gate 346. The AND gate342 and the OR gate 346 supply their output signals respectively via theRST ENB H signal lines 260 a and 260 b through resistors 352 and 354 toinputs of Schmitt triggers 356 and 358. Capacitors 362 and 364 arerespectively connected between circuit ground and the junction of theresistors 352 and 354 with the inputs to the Schmitt triggers 356 and358. The other inputs of the Schmitt triggers 356 and 358 are connectedto Vcc. Analogous to the NOR gates 326 and 328, each of the Schmitttriggers 356 and 358 supplies its output signal to inputs of the ANDgates 342 and 344 respectively via RST DEL L signal lines 368 a and 368b. The Schmitt triggers 356 and 358 and the signal lines 368 a and 368 bcross-couple the AND gates 342 and 344 in a manner similar to thecross-coupling of the NAND gates 312 and 314, and AND gates 322 and 326described above. Similar to the arbitration-latches for the SEL, DB0-DB7and DBP signals of the SCSI buses, the BUS CONNECTED L signal line 274 bconnects to inputs of the AND gates 342 and 344.

[0089] The third input to the AND gate 342 connects to the RST IN Lsignal line 236 a from the shared interface card 48 while 25 the thirdinput to the AND gate 344 connects to the RST IN L signal line 236 bfrom all the sharing interface cards 48. Differing from thebidirectional repeaters for the SEL, DB0-DB7 and DBP signals of the SCSIbuses, the switched transceiver circuit 130 for the SCSI bus' RST signallacks an “OUT L” signal line. Consequently, the signal present RST IN Lsignal line of one interface card 48 cannot become an input signal tothe transmitting buffer 138 in the switched transceiver circuits 130 ofthe other interface card 48. Rather the inputs of both transmittingbuffers 138 in the switched transceiver circuits 130 of both interfacecards connect to circuit ground. The connection of the inputs of bothtransmitting buffers 138 to circuit ground is necessary because the SCSIbus' RST signal line carries a wire-OR signal that can be simultaneouslyasserted by as many as all devices connected to the bus. Connecting theinput of the transmitting buffer 138 to circuit ground causes the buffer138 to assert its output signal when it is enabled by the RST ENB Hsignal on the signal line 260 and to let the RST signal line float freeto be negated by the termination resistors 154 and 156 after thetransmitting buffer 138 is disabled.

[0090] If the Schmitt triggers 356 and 358, the resistors 352 and 354and the capacitors 362 and 364 were omitted from the arbitration-latchfor the SCSI bus' RST signal, then differences in RST signal'spropagation delays through one of the AND gates 342 or 344 and theswitched transceiver circuits 130 back to the AND gates 344 or 342 couldproduce a pulse that circulates forever within the bidirectionalrepeater. Such a pulse circulating within the bidirectional repeaterwould, of course, repetitively present all the devices connected to bothSCSI buses with a RST signal each time the pulse went around thecircuit. The combined Schmitt triggers 356 and 358, the resistors 352and 354 and the capacitors 362 and 364 delay the propagation of thesignals from the outputs of the AND gate 342 and the OR gate 346 to theinputs respectively of the AND gates 342 and 344 sufficiently long tosuppress generation of a circulating pulse.

[0091] The arbitration-latch for the SCSI bus' RST signal differs fromall other arbitration-latches in the bus switch 40 by being asymmetric.That is, the output signal from the AND gate 342 goes directly to theresistor 352 whereas the output signal from the AND gate 344 passesthrough the OR gate 346 before application to the resistor 354. Anotherasymmetry in this arbitration-latch is the four inputs of the AND gate342 versus the three inputs of the AND gate 344. The bus switch 40includes this asymmetry to permit a RESET SHARED DEVICES ON SELECTION Lsignal, supplied from the bus switch state sequencer 302 to an input ofthe OR gate 346 via a RESET SHARED DEVICES ON SELECTION L signal line382, to cause all SCSI devices connected to the shared data bus 58 to bereset upon enabling one of the sharing interface cards 48. Applicationof this same RESET SHARED DEVICES ON SELECTION L signal to the fourthinput of the AND gate 342 prevents assertion of the RST signal on theshared data bus 58 from propagating through the RST signal'sarbitration-latch to the enabled sharing data bus 52, 54 or 56.

[0092] The other bidirectional repeaters included in the bus switch 40for the SCSI bus' C/D, I/O, MSG, REQ, ACK and ATN are not used in theSCSI bus's ARBITRATION phase. Of these six signals, only the SCSI bus'I/O signal participates in the bus' SELECTION or RESELECTION phases inwhich the signal originates at the winning arbitrating device. Inaddition, during all phases of the SCSI bus protocol other than BUS FREEand ARBITRATION phases, the initiator may, at any time, assert ATN towhich the target may optionally respond by executing a MESSAGE OUT phaseof the SCSI bus protocol. Finally, during the SCSI bus' informationphases the signals REQ, I/O, C/D AND MSG pass only from the target tothe initiator device while, conversely, the ATN and ACK signals passonly from the initiator to the target. Consequently, the bidirectionalrepeaters for those signals do not require an arbitration-latch such asthose included on the control card 44 for the SEL, DB0-DB7, DBP and RSTsignals. Rather, as illustrated in FIG. 5, the relevant signal lines 242and 244 pass directly through the control card 44 between the shared businterface card connector 46 a and the sharing bus interface cardconnector 46 b.

[0093] Other than for the SCSI bus' I/O signal present on the I/O IO Lsignal line 242, none of the other signals present on the four signallines 242 and the two signal lines 244 passing through the control card44 influences the operation of the bus switch 40. With regard to theSCSI bus' I/O signal, that signal is used in controlling the operationof the bus switch 40. Accordingly, FIG.B 5 illustrates that only the I/OIO L signal line 242, of the four signal lines 242, connects to the busswitch state sequencer 302.

[0094] The preceding description of the various bidirectional repeaters,both those that include and those that lack an arbitration-latch, hasencompassed all of the SCSI bus' signals except its BSY signal. For theBSY signal, the bus switch state sequencer 302 receives the signalspresent on the BSY IN L signal lines 232 a and 232 b respectively fromboth the shared bus interface card 48 and from all the sharing businterface cards 48. Digital logic in the switch state sequencer 302processes the BSY signals received from both SCSI buses via the sharedbus interface card 48 and the enabled sharing bus interface card 48 toproduce two BSY ENB H control signals. The bus switch state sequencer302 transmits one BSY ENB H control signal to the transmitting buffer138 of the switched transceiver circuit 122 in the shared bus interfacecard 48 and the other BSY ENB H control signal to the enabled sharingbus interface card 48 respectively via the BSY ENB H signal lines 252 aand 252 b. Because, similar to the RST signal, the SCSI bus's BSY signalline is a wire-OR signal, the input of the transmitting buffer 138 ofthe switched transceiver circuit 122 connects to circuit ground the sameas the connection of the transmitting buffer 138 in the switchedtransceiver circuit 130 for the SCSI bus' RST signal. Accordingly,similar to the switched transceiver circuit 130 for the RST signal, theswitched transceiver circuit 122 never actively negates the BSY signal.The following discussion of the bus switch state sequencer 302 morefully explains its operation for generating these two BSY ENB H signalstogether with other signals for controlling the operation of the busswitch 40.

[0095] Bus Switch State Sequencer 302

[0096]FIG. 6, made up of FIGS. 6a and 6 b, is a logic diagram depictingthe bus switch state sequencer 302 that is included in the control card44. Depicted in FIG. 6 is a circuit for disabling the operation of thebus switch 40 for a short interval after it initially receiveselectrical power and until that power stabilizes. This circuit, locatedin the bus switch state sequencer 302, includes a Schmitt trigger 402that transmits a DC OK L signal to all of the interface cards 48 via theDC OK L signal line 278. To sense the state of the electrical power inthe bus switch 40, one input of Schmitt trigger 402 connects directly toVcc while its other input connects to Vcc through a parallel networkmade up of a resistor 404 and a diode 406 that has its anode connectedto the input of the Schmitt trigger 402 and its cathode connected toVcc. In addition to the resistor 404 and the diode 406, this input ofthe Schmitt trigger 402 connects to one terminal of a capacitor 408, theother terminal of which connects to circuit ground. When power is firstapplied to the bus switch 40, output signal from the Schmitt trigger 402is negated. Subsequently while power continues to be applied to the busswitch 40, current, flowing through the resistor 404, charges thecapacitor 408 above the threshold of the Schmitt trigger 402. When thevoltage on the capacitor 408 exceeds the Schmitt trigger's threshold,its DC OK L output signal is asserted thereby enabling the interfacecards 48 to respond to signals from the control card 44, to signals onthe SCSI bus 52-58 to which the interface cards 48 respectively connect,and to a signal from the toggle switch 84 on the shared bus-requestcables 78 that are respectively associated with the sharing SCSI buses52-56 or to a signal from the selector switch 88 illustrated in FIG. 3.

[0097] In addition to the circuit for disabling the operation of the busswitch 40, the bus switch state sequencer 302 depicted in FIG. 6includes a latching-sequencer and a decoder/encoder that, in response tosignals occurring on the shared data bus 58 and the enabled one of thesharing data buses 52, 54 or 56, generates output signals which controlthe operation of the bus switch 40. In the preferred embodiment of theinvention, most of the logic circuitry depicted in FIG. 6 actuallyresides in a plurality of PALs to be described in greater detail below.In addition to that portion of the logic circuitry depicted in FIG. 6which resides in the plurality of PALs, all of the gates 312, 314, 322,324, 326, 328, 342, 344 and 346 depicted in FIG. 5 also reside in thosesame PALs. Accordingly, the logic diagrams of FIGS. 5 and 6 illustratethe construction of the bus switch 40 from a pedagogical viewpointrather than conforming to the actual implementation of the preferredembodiment. To increase comprehension, the logic circuitry depicted inFIG. 6 omits or simplifies certain details of the actual implementationof the bus switch 40. e.g. details related to logic minimization and tothe elimination of logic “hazards,” even logic hazards arising fromtransitions between phases of the SCSI bus protocol. Moreover, the logicdiagram of FIG. 6 also omits details related to circuit loading such asline drivers included in the preferred embodiment for the signal linesRPLY IN H 266 a and 266 b, RPLY OUT H 258 a and 258 b, CTL IN H 264 aand 264 b, CTL OUT H 256 a and 256 b, BSY ENB H 252 a and 252 b.However, while FIG. 6 does not precisely depict the structure of thepreferred embodiment, the detailed structure of the portion of thecontrol card 44 residing in the PALs is expressly set forth in theirdescription below. Accordingly, in the following discussion of FIG. 6all logic devices that are not expressly referred to by a referencenumber reside in one of the PALs.

[0098] To allow the bus switch 40 to properly transmit signals betweenthe shared data bus 58 and the enabled sharing data bus 52, 54 or 56,the bus switch state sequencer 302 operates in the following manner.Assuming that both the shared data bus 58 and the enabled sharing databus 52, 54 or 56 are in the BUS FREE phase of the SCSI bus' protocol,the bus switch state sequencer 302 is in a quiescent state receiving thenegated BSY signals both from the bus 58 and from one of the buses 52,54 or 56. If one or more devices on the shared data bus 58 asserts BSY,the bus switch state sequencer 302 responds by causing the transmittingbuffer 138 in the enabled sharing bus interface card 48 to assert BSY onthe BSY control signal line 102 in the enabled sharing data bus 52, 54or 56. The associated receiving buffer 136 of the enabled sharinginterface card 4B then receives this assertion of the BSY signal fromthe transmitting buffer 138 via the BSY control signal line 102 andfeeds that signal back to the bus switch state sequencer 302. Inresponse to this assertion of the BSY signal, the bus switch statesequencer 302 causes the transmitting buffer 138 in the shared businterface card 48 to also assert BSY on the shared data bus 58 togetherwith the arbitrating device connected thereto. Feedback of the assertedBSY signal from this transmitting buffer 138 via the BSY control signalline 102 of the shared data bus 58 to the associated receiving buffer136 then latches the BSY signal on both of the composite buses 52-58,54-58 or 56-58 in the asserted state regardless of subsequent negationof the BSY signal by all arbitrating devices. Conversely, if the deviceasserting BSY were rather located on the enabled sharing data bus 42, 54or 56, the bus switch 40 operates the same except that the feedbackoccurs first between the transmitting buffer 138 and the receivingbuffer 136 of the shared interface card 48 and then between the buffers138 and 136 of the enabled sharing interface card 48. Consequently,during the ARBITRATION phase of the SCSI bus's protocol, irrespective ofthe location on the buses 52-58 of an arbitrating device, the bus switch40 always asserts and latches BSY on both buses of the composite bus52-58, 54-58 or 56-58 in addition to the assertion of BSY on one or bothof them by arbitrating devices. This multiple assertion of BSY signalsboth by the arbitrating device and by the bus switch 40 causes noproblem because the SCSI bus' BSY signal Sine is a wire-OR signal line.

[0099] The bus switch 40 asserts the BSY signal both on tle shared databus 58 and on the enabled sharing data bus 52, 54 or 56 to prevent aglitch in the BSY signal if the device that first asserted its BSYsignal loses the arbitration to another device that is on the oppositeside of the bus switch 40. If the bus switch 40 did not assert the BSYsignal on both buses but rather, transmitted it through a bidirectionalrepeater such as that for the SEL signal, then when the losing devicethat began the arbitration by asserting its BSY signal subsequentlynegated that signal because it lost the arbitration, the BSY signal onthat device's bus would be negated for a brief interval until thebidirectional repeater switched to drive the BSY signal in the oppositedirection. The bus switch 40 avoids the possibility of such a glitch inthe BSY signal by asserting the BSY signal on both the shared data bus58 and on the enabled sharing data bus 52, 54 or 56.

[0100] Concurrent with receipt of the BSY signal by the bus switch 40and its retransmission of that signal onto both buses, the bidirectionalrepeaters for the SCSI bus' DB0-DB7 signals also appropriatelyretransmit the assertion of any of those signals from the bus 52, 54, 56or 58 on which they are asserted onto the bus 52, 54, 56 or 58 on whichthey are not asserted. Unidirectional transmission of the SCSI bus'DB0-DB7 signals by the bidirectional repeaters is necessary because theSCSI bus' DB0-DB7 signal lines do not carry wire-OR signals.Accordingly, during the SCSI bus' ARBITRATION phase, the bidirectionalrepeaters for the SCSI bus signals DB0-DB7 may transmit one of thosesignals from the shared data bus 58 to the enabled sharing data bus 52,54 or 56 while another one of the DB0-DB7 signals is transmitted in theopposite direction.

[0101] Shortly before the end of the SCSI bus' ARBITRATION phase, thewinning arbitrating device asserts the SCSI bus' SEL signal which passesthrough the bidirectional repeater included in the bus switch 40 for theSEL signal. Assertion of the SCSI bus' SEL signal by the winningarbitrating device reveals to the bus switch state sequencer 302 onwhich side of the bus switch 40 the winning device is located.Accordingly, immediately after assertion of the SCSI bus' SEL signal,the bus switch state sequencer 302 breaks the feedback path and removesits assertion of the BSY signal on the bus 52, 54, 56 or 58 on which thewinning device is located and, responsive to assertion of the BSY signalby the winning device, continues to assert that signal only on the otherbus 52, 54, 56 or 58, on which a subsequently selected 30 device may belocated. When the bus switch 40 terminates its assertion of the BSYsignal on the bus 52, 54, 56 or 58 on which the winning device islocated, it thereby unlatches assertion of the BSY signal.

[0102] Because the ARBITRATION phase of the SCSI bus' protocol isfollowed by either a SELECTION phase or a RESELECTION phase during whichthe winning device indicates which of those particular phases bynegating or asserting the I/O signal, and because the winning device maybe an initiator capable of asserting the ATN signal during the SELECTIONphase, during the SELECTION or RESELECTION phase the C/D IO L, I/O IO L,MSG IO L and REQ IO L switched transceivers 126 and the ACK and ATNswitched transceivers 128 on both the shared and enabled sharinginterface cards 48 are all enabled to transmit signals only from the bus52, 54, 56 or 58 on which the winning device is located to the bus 52,54, 56 or 58 on which the selected device may be located. (Note, thepreceding operation of the bus switch state sequencer 302 with respectto the common transmission direction for the C/D, I/O, MSG and REQcontrol signal lines 106 and the ACK and ATN control signal lines 108,while slightly simplifying the digital logic included in the sequencer302, does not strictly follow the ANSI specification for the SCSI bus.The preceding operation is in accordance with the ANSI specificationduring the SELECTION phase, but contravenes the ANSI specificationduring the RESELECTION phase. Strict accordance with the ANSIspecification requires that the ATN control signal line 108 be enabledfor transferring signals from the selected device to the winning deviceduring the RESELECTION phase of the SCSI bus protocol, rather than fromthe winning device to the selected device. Thus far, experimentaltesting of a bus switch 40 constructed in accordance with thedescription set forth herein has not revealed any operationaldifficulties arising from this deviation from the ANSI specification.Furthermore, if operational difficulties do arise in the future fromthis aspect in the operation of the bus switch 40, only a minor changeis required in the digital logic of the bus switch state sequencer 302to conform its operation to the ANSI specification.)

[0103] During the SELECTION or RESELECTION phases of the SCSI bus'protocol, the winning device continues to assert the SCSI bus' SELsignal while negating the SCSI bus' BSY signal and simultaneouslyasserting its address and the address of the device it wishes to selecton the SCSI bus' DB0-DB7 signal lines. Assertion of the SCSI bus' BSYsignal during the SELECTION phase of the SCSI bus' protocol by theselected device in response to the winning device's assertion of the SELsignal reveals, to the bus switch state sequencer 302, the selecteddevice's location on one side or the other of the bus switch 40. Inresponse to assertion of the SCSI bus's BSY signal by the selecteddevice, the bus switch state sequencer 302 once again, as at it did atthe beginning of the ARBITRATION phase, causes the bus switch 40 toassert BSY both on the shared data bus 58 and on the enabled sharingdata bus 52, 54 or 56. As set forth above, assertion of the SCSI bus'BSY signal on both buses 52 and 52, 55 or 56 during the SELECTION orRESELECTION phases of the SCSI bus protocol causes no problem becausethe BSY signal line is a wire-OR signal. Moreover, during theRESELECTION phase of the SCSI bus protocol, both the winning device andthe selected device simultaneously assert the SCSI bus's BSY signal. Atthe end of the SCSI bus' SELECTION phase when the winning device negatesSEL, the bus switch state sequencer 302 removes its assertion of BSYfrom the bus 52, 54, 56 or 58 on which the selected device is locatedthereby again unlatching assertion of the BSY signal and giving solecontrol of the BSY signal to the selected device. At the end of the SCSIbus' RESELECTION phase when the winning device negates SEL and assertsBSY, the bus switch state sequencer 302 removes its assertion of BSYfrom the bus 52, 54, 56 or 58 on which the winning device is locatedthereby again unlatching assertion of the BSY signal and giving solecontrol of the BSY signal to the winning device.

[0104] From the preceding description of the responses of the bus switch40 to signals during the SCSI bus' ARBITRATION and SELECTION orRESELECTION phases, it is apparent that during those phases, digitallogic circuits, included in a latching-sequencer 410 of the bus switchstate sequencer 302 that is enclosed within a dashed rectangle in FIG.6, store information indicating whether the initiator and target areboth on the shared data bus 58, whether the initiator and target areboth on one of the sharing data buses 52, 54 or 56, whether theinitiator is on the shared data bus 58 with the target on one of thesharing buses 52, 54 or 56, or whether the initiator is on one of thesharing buses 52, 54 or 56 and the target is on the shared data bus 58.Since in only the third and fourth instances listed above will datatransmission pass between the devices through the bus switch 40, only inthose instances must the bus switch 40 respond further to signals on theSCSI bus until the next BUS FREE phase occurs. However, in the preferredembodiment of the bus switch 40 in the first and second instances thesignals on the single bus 52, 54, 56 or 58 to which both devices connectare transmitted through the bus switch 40 to the other bus 52, 54, 56 or58. In the third and fourth instances listed above, the informationobtained by the bus switch state sequencer 302 during the ARBITRATIONand SELECTION or RESELECTION phases allows it to provide control signalsthat properly configure the shared interface card 48 and the enabledsharing interface card 48 for exchanging data between the shared databus 58 and the enabled sharing data bus 52, 54 or 56 during thesubsequent information exchange phases. Accordingly, in the third andfourth instances at the end of the SELECTION phase the bus switch statesequencer 302 enables the switched transceiver circuits 126 for the C/D,I/O, MSG, and REQ control signal lines 106 to transfer signals from thetarget to the initiator, and enables the switched transceiver circuits128 for the ACK and ATN control signal lines 108 to transfer signalsfrom the initiator to the target.

[0105] To identify the locations of the initiator and target of a SCSIbus data transmission during the ARBITRATION and SELECTION orRESELECTION phases of the SCSI bus' protocol and to store thatinformation for use during subsequent information phases, the bus switchstate sequencer 302 includes a plurality of latches within the sequencer410 arranged vertically on the left hand side of FIG. 6. These latchesrespond to signals on the SEL ENB H signal lines 254 a and 254 b whichrespectively come from the outputs of the NAND gates 314 and 312. Thelatches also respond to signals on the BSY IN L signal lines 232 a and232 b after those signals have been ORed together in a NOR gate 412 toproduce a BSY A+B signal on a BSY A+B B signal line 414. In addition toconnecting to the latches of the sequencer 410, the BSY A+B H signalline 414 connects to the inputs of a pair of monostable multivibrators416 and 418.

[0106] Via a BSY DOWN TIMER H signal line 419, the monostablemultivibrator 416 transmits a four millisecond pulse upon assertion ofthe BSY signal on either the shared data bus 58 or the enabled sharingdata bus 52, 54 or 56. If the bus switch 40 latches both SCSI bus BSYsignal lines in the asserted state in response to a glitch on either BSYIN L signal line 232 a or 232 b, such as that produced by AppleComputer's Macintosh when it is turned on, expiration of the fourmillisecond interval established by the monostable multivibrator 416negates the BSY ENB H signals from both signal lines 252 a and 252 b.Negating the BSY ENB H signals from the signal lines 252 a and 252 bdisables the transmitting buffers 138 in both switched transceivercircuits 122 in the shared bus interface card 48 and in the enabledsharing bus interface card 48. Disabling both of the transmittingbuffers 138 at the end of the four millisecond interval returns the SCSIbus once again to its BUS FREE phase. Thus, the monostable multivibrator416 prevents latching up the SCSI bus's BSY signal lines in response toglitches on those signal lines.

[0107] Via a BSY UP TIMER H signal line 420, the monostablemultivibrator 418 transmits a four hundred nanosecond pulse upon thenegation of the BSY A+B signal, i.e. upon the negation of both BSYsignals from the shared data bus 58 and the enabled sharing data bus 52,54 or 56. In accordance with the ANSI standard for the SCSI bus, theoutput signal from the monostable multivibrator 418 inhibits the busswitch state sequencer 302 from responding to the negation of SCSI bus'BSY control signal line 102 unless and until the BSY control signal line102 has been negated continuously for four hundred nanoseconds.

[0108] In addition to the signals on the signal lines 254 a, 254 b, 232a and 232 b, the latches of the sequencer 410 also respond to a signalpresent on the SEL A IN L to SEL B OUT L signal line 316, and to asignal on the I/O IO L signal line 242. (Recall that as described above,the I/O IO L signal line 242 is the only one of the four signal lines242 that influences the operation of the bus switch 40.) Finally, thelatches of the sequencer 410 respond to signals from the several sharingbus interface cards 48 on the CHANGE REQUESTED L signal line 272 b andon the BUS CONNECTED L signal line 274 b.

[0109] Within the bus switch state sequencer 302, a SELECT L signal line422 connects an output from a latch located within one of the PALs to aninput of a monostable multivibrator 424. The monostable multivibrator424 transmits a four millisecond long pulse on a RESET TIMER L signalline 425 whenever a new sharing bus interface card 48 is selected. Amongother things, if a jumper 426 is installed on the bus switch statesequencer 302, the pulse generated by the monostable multivibrator 424is transmitted from the RESET TIMER L signal line 425 to thearbitration-latch for the SCSI bus' RST signals via the RESET SHAREDDEVICES ON SELECTION L signal line 382. In this way, a pulse on theRESET SHARED DEVICES ON SELECTION L signal line 382 resets all devicesconnected to the shared data bus 58 upon enabling one of the sharinginterface cards 48.

[0110] Within the bus switch state sequencer 302, the latches of thesequencer 410 located along the left hand side of FIG. 6 produce severaloutput signals that are applied as input signals to encoders 432 a and432 b and to a decoder/encoder 434 which are located along the righthand side of FIG. 6 and respectively enclosed within dashed rectangles.The encoders 432 a and 432 b and the decoder/encoder 434 produce outputsignals from the bus switch state sequencer 302 that control theoperation of the bus switch 40 in response to signals on the SCSI buses52-58. Thus the encoder 432 a produces the BSY ENB H signals that arerespectively transmitted via the BSY ENB H signal lines 252 a and 252 brespectively to the switched transceiver circuits 122 located in theshared bus interface card 48 and in all the sharing bus interface cards48. The encoder 432 b produces the DATA A TO B L and DATA B TO A Lsignals that are respectively transmitted over the DATA A TO B L signalline 336 a and the DATA B TO A L signal line 336 b to inputs of the NORgates 328 and 326 included in each of the nine arbitration-latches forthe SCSI bus' DB0-DB7 and DBP signal lines.

[0111] The decoder/encoder 434 included in bus switch state sequencer302 produces the CTL IN H signals transmitted over the CTL IN H signallines 264 a and 264 b and the CTL OUT H signals transmitted respectivelyover the CTL OUT H signal lines 256 a and 256 b. The signals transmittedover the signal lines 264 a and 256 a, and 264 b and 256 b control theoperation of the switched transceiver circuits 126 for the SCSI bus'sC/D, I/O, MSG and REQ signals respectively on the shared bus interfacecard 48 and on the sharing bus interface cards 48. The decoder/encoder434 also produces the RPLY IN H signals transmitted respectively overthe RPLY IN H signal lines 266 a and 266 b and the RPLY OUT H signalstransmitted respectively over the RPLY OUT H signal lines 258 a and 258b. The signals transmitted over the signal lines 266 a and 258 a, and266 b and 258 b control the operation of the switched transceivercircuits 128 for the SCSI bus's ACK and ATN signals respectively of theshared and of the sharing bus interface cards 48.

[0112] Various signals both from outside and inside the bus switch statesequencer 302 influence the output signals from the encoders 432 a and432 b and also the decoder/encoder 434. Thus, the SCSI bus's SEL signalon the shared data bus 58 that is supplied to the bus switch statesequencer 302 on the SEL A IN L to SEL B OUT L signal line 316influences the output signals from the encoders 432 a and 432 b and alsothe decoder/encoder 434. Similarly, the initiator's SCSI bus' I/O signalsupplied to the bus switch state sequencer 302 on the I/O IO L signalline 242 influences the output signals of the encoders 432 a and 432 band also the decoder/encoder 434. Correspondingly, the bus switch's BUSCONNECTED L signal on line 274 b supplied to the bus switch statesequencer 302 on the BUS CONNECTED L signal line 274 b from the enabledsharing interface card 48 influences the output signals from theencoders 432 a and 432 b and also the decoder/encoder 434. Finally,various other signals produced internally within the bus switch statesequencer 302 by the latching-sequencer 410 also influence the outputsignals from the encoders 432 a and 432 b and also the decoder/encoder434.

[0113] One of the signals produced by the latching-sequencer 410 is anIDLE+ARB signal that is supplied to the encoders 432 a and 432 b and thedecoder/encoder 434 via an IDLE+ARB L signal line 442. When both theshared data bus 58 and the enabled sharing data bus 52, 54 or 56 are inthe BUS FREE phase of the SCSI protocol, the IDLE+ARB signal is forcedinto the asserted state (low). When at the commencement of the SCSI bus'ARBITRATION phase when the bus' BSY signal is asserted by an arbitratingdevice, the IDLE+ARB signal becomes latched in its asserted state. TheIDLE+ARB signal remains latched in the asserted state throughout theremainder of the ARBITRATION phase and into the SELECTION or RESELECTIONphase until the BSY signal has been negated and the time intervalcreated by the monostable multivibrator 418 in response to negation ofthe BSY signal expires. At the expiration of the time interval createdby the monostable multivibrator 418, the IDLE+ARB signal is forced intothe negated state (high) to be latched in that state at the end of theSELECTION or RESELECTION phase when the SCSI bus' BSY signal isreasserted. Alternatively, in a non-arbitration SCSI bus system having asingle initiating device the IDLE+ARB signal is forced into the assertedstate during the BUS FREE phase of the SCSI bus protocol before a deviceasserts its SEL signal to start a transaction. Upon assertion of theSCSI bus' SEL signal in a non-arbitration system, the IDLE+ARB signal isnegated and then latched in that state at the end of the SELECTION phaseupon the assertion of the SCSI bus' BSY signal.

[0114] Another signal that the encoders 432 a and 432 b and thedecoder/encoder 434 receive from the latching-sequencer 410 via a BSYA+B DELAYED L signal line 444 is the BSY A+B DELAYED signal. This signalis merely the OR of the BSY signals from the shared data bus 58 and theenabled sharing data bus 52, 54 or 56.

[0115] The encoders 432 a and 432 b and the decoder/encoder 434 alsoreceive a WINNER A signal from the latching-sequencer 410 via a WINNER AL signal line 446. If the winning arbitrating device is connected to theshared data bus 58, then at the beginning of the SCSI bus' SELECTIONphase the SEL signal line on the bus 58 is asserted. Assertion of theSEL signal on the bus 58 during the SCSI bus's SELECTION phase causesthe signal on the WINNER A L signal line 446 to be latched in theasserted state. If the signal on the WINNER A L signal line 446 islatched in the asserted state, it will remain in that state as long aseither the BSY signal or the SEL signal remains asserted on thecomposite bus made up of the shared data bus 58 and the enabled sharingdata bus 52, 54 or 56, i.e. for the rest of the transaction.

[0116] The latching-sequencer 410 also transmits a SELECTED DEVICE Asignal to the encoders 432 a and 432 b and the decoder/encoder 434 via aSELECTED DEVICE A L signal line 448. The signal on the SELECTED DEVICE AL signal line 448 latches in the asserted state if the bus switch statesequencer 302 receives a BSY signal first from the shared data bus 58during the brief interval in the SELECTION phase of the SCSI bus'protocol before the sequencer 302 receives the retransmission of thatsignal back from the enabled sharing data bus 52, 54 or 56. If thesignal on the SELECTED DEVICE A L signal line 448 is latched in theasserted state, it will remain in that state as long as either the BSYsignal or the SEL signal remains asserted on the composite bus made upof the shared data bus 58 and the enabled sharing data bus 52, 54 or 56,i.e. for the rest of the transaction.

[0117] Another signal that the encoders 432 a and 432 b and thedecoder/encoder 434 receive from the latching-sequencer 410 via aRESELECT L signal line 452 is the RESELECTION signal. This signal islatched in the asserted state if the SCSI bus' I/O signal is asserted bythe winning device in the SCSI bus phase immediately following theARBITRATION phase. Latched in the asserted state, the RESELECTION signalindicates that a SCSI bus RESELECTION is taking place rather than aSELECTION. In accordance with the SCSI bus' ANSI standard, after aRESELECTION the winning device becomes the target and the selecteddevice is the initiator. If the signal on the RESELECT L signal line 452is latched in the asserted state, it will remain in that state as longas either the BSY signal or the SEL signal remains asserted on thecomposite bus made up of the shared data bus 58 and the enabled sharingdata bus 52, 54 or 56, i.e. for the rest of the transaction.

[0118] Once the states of the WINNER A, SELECTED DEVICE A, andRESELECTION signals have all been latched by the end of the SELECTIONphase of the SCSI bus protocol, the encoders 432 a and 432 b and thedecoder/encoder 434 then produce appropriate signals on the signal linesRPLY IN H 266 a and 266 b, RPLY OUT H 258 a and 258 b, CTL IN H 264 aand 264 b, CTL OUT H 256 a and 256 b, BSY ENB H 252 a and 252 b tocontrol the operation of the bus switch 40 during subsequent phases ofthe transaction until the SCSI bus once again returns to the BUS FREEphase with BSY and SEL unasserted.

[0119] Programmable Array Logic

[0120] As described above, in the preferred embodiment of the presentinvention, most of the digital logic circuitry on the control card 302is implemented with PALS. The following table lists those PALs andprovides a brief description of their function. The type numbers setforth in the table below are JEDEC designations for PALs such as thosemanufactured by Monolithic Memories Inc. (“MMI”). Type 2217 is an MMI16L8, and type 2226 is an MMI 20L8. Each of the IC nos. listed belowassociate a particular PAL with a subsequent signal line to pin numberassignment table, and with a subsequent PAL map listing. IC No. TypeFunction U1 2226 Arbitration-latches for SCSI bus DB0-DB3 signal linesU2 2217 Arbitration-latches for SCSI bus RST, SEL and DBP signal linesexcluding the Schmitt triggers 356 and 358 of the RST signal'sarbitration-latch U5 2226 Arbitration-latches for SCSI bus DB4-DB7signal lines U6 2217 Encoder/decoder 424 U8 2217 Decoder 432b and theportion of the latching-sequencer 410 that controls interface cardselection excluding the monostable multivibrator 424 U10 2217 Decoder432a and the portion of the latching-sequencer 410 that controls busstate sequencing excluding the NOR gate 412 and the monostablemultivibrators 416 and 418

[0121] The preceding PAL type numbers are for PALs manufactured byMonolithic Memories Inc. The following table lists the reference numbersof signal lines described in the preceding text and specifies theparticular pin numbers of the various PALs to which that signal lineconnects. In the following table, the notation “(L)” indicates that anoutput signal from the PAL is supplied to an inverter external to thePAL and that the output from the inverter connects to the signal lineidentified by the signal line reference number. Also, the numbers 0-7and the letter “P” indicate the particular data lines and parity line inthe DATA BUS portion of the SCSI bus. Signal Line PAL Pin No. ReferenceNo. U1 U2 U5 U6 U8 U10 232a 11 232b 9 236a 9 236b 2 242 8 8 7 252a 19(L)252b 12(L) 254a 14 4 254b 15 3 256a 12(L) 256b 16(L) 258a 13(L) 258b17(L) 260a 12 260b 19 262a n = 0 20 n = 1 19 n = 2 18 n = 3 17 n = 4 20n = 5 19 n = 6 18 n = 7 17 n = P 17 262b n = 0 23, 22 n = 1 21 n = 2 16n = 3 14, 15 n = 4 22, 23 n = 5 21 n = 6 16 n = 7 14, 1 15 n = P 18 264a14(L) 264b 18(L) 266a 15(L) 266b 19(L) 272 16 274 13 16 13 11 11 8 27615 13 316 7 2 2 318 6 332 n = 0 4 n = 1 5 n = 2 9 n = 3 10 n = 4 4 n = 55 n = 6 9 n = 7 10 n = P 4 334 n = 0 2 n = 1 3 n = 2 7 n = 3 8 n = 4 2 n= 5 3 n = 6 7 n = 7 8 n = P 3 336a 6 8 6 19 336b 11 5 11 18 368a 11 368b1 382 13 414 1 419 6 420 5 422 13 425 1 442 4 4 17 444 3 3 18 446 5 5 16448 6 6 15 452 7 7 14 462 14

[0122] Control Card PAL ICs U1 and U5 - Data Repeaters *D2226*F0* L00001111111111111111111111111111111111111111111111111111110101111111111111111111111111111111011111110111111111111111111111111111111111111111111111111111111111111101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111111111111111111111111111111010111111111111111111111111111111111011101111111111111111111111111111111111111111111111111111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111111111111111111111111111111111101111111111111111111111111111101110111111111111111111111111111111111110111111111111111111111111111111111111111110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111101111111111111111111111111011111110111111111111111111111111111111101111111111111111111111111111111111111111101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111110111110111111111111111111111110111111111111111011111111111111111111111111111111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111111111111111111111111111111111111111111111111111111111111110101111111111111111111111111110111111111110111111111111111111111111111111111111111110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111101111101111111111111111111111111111111110111111111110111111111111111111111111111111111111111111111111101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111111111111111111111111111111011111111101111111111111111111111111111101111111111111110111111111111111111111111111111111111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *C9B84* Control Card PAL ICU2 - Control Signal Repeaters *D2217*F0* L000011111111111111111111111111111111 1111111111111101111111111111111111111111111111111111111111101111 1111111111111111111111111111111011111111111111111111111111110111 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111101111111111111110111111111111111110111111111111101111111 1111111111111101111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111011111110111111111111111111111111101111101111111111111111111 1111111111111101111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111111111101111111111111111111111111111111111111011111111111 1111111111111111111111011111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111111111101111111111111111111111111111111110111111111111111 1111111111111111110111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1110111111111111111111111101111101111111111111111111111111011111 1111111111111101111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000*C60A7* Control Card PAL IC U6 - Buffer Enable Decoders *D2217*F0* L000011111111111111111111111111111111 0111101101111011011110111111111001111011011101110111111111111110 1111101101110111111101111111111010111111111101111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101111011011101111111111001111011011101111011101111111110 0111101101110111011111111111111010111111111101111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101110111101110111111111001111011011110111011111111111110 1111101101111011111101111111111010111111111110111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101110111101101111111111001111011011110110111101111111110 0111101101111011101111111111111010111111111110111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101110111101110111111111001111011011110111011111111111110 1111101101111011111101111111111010111111111110111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101110111101101111111111001111011011110110111101111111110 0111101101111011101111111111111010111111111110111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101111011011110111111111001111011011101110111111111111110 1111101101110111111101111111111010111111111101111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101111011011101111111111001111011011101111011101111111110 0111101101110111011111111111111010111111111101111111111111111110 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000*C8786* Control Card PAL IC U8 - Selection Logic *D2217*F0* L000011111111111111111111111111111111 0111101101111011011101111011111001111011011101111011011101111110 0111101101111011011110110111111001111011011101111011101110111110 0111101101111011101111111111111000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 0111101101111011011101110111111001111011011101111011011110111110 0111101101111011011110111011n1001111011011101111011101101111110 0111101101110111011111111111111000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1110111111111111111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1101111111101111111111111110111111111111111111101111111011111101 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111111111110111011011111110111111111111111111111110111101111 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000*C44E5* Control Card PAL IC U10 - Sequencer *D2217*F0* L000011111111111111111111111111111111 1111101110101111011111111011101111111111110111101101110110111011 1111111111011101111011101011101111111011011011111111111110111011 1111011110011111111111111011101111111111110111011101111110111011 0000000000000000000000000000000011111111111111111111111111111111 1101111111111111111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111011101111111111111111111111111111111001111111111111111111 1111111111111111111111111110111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111011110101111111111111011111111110111101111101111111110111111 1111111011111110111111111011111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111100101011111111111111011111011110101100111111111111110111110 1111111011111111111011111011111111111111111101111110111110111111 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111101101011111111101111011111111110111100111111111011110111111 1111111011111111111111101011111111111111111101111111111010111111 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111100110111011111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111101110101111011111111011111011111111110111011110110110111110 1111111111011110110111101011111011110111101011111111111110111110 1111101101011111111111111011111011111111110111101110111110111110 00000000000000000000000000000000*C7F92*

[0123] Interface Card PAL 162

[0124] Referring now to FIG. 6, the latching-sequencer 410 transmits aPRI OUT signal from the bus switch state sequencer 302 on a PRI OUT Lsignal line 462 to a plug 464 depicted in FIG. 5. A cable within the busswitch 40 (not depicted in any of the FIGS.) connects to the plug 464and extends the PRI OUT L signal line 462 from the control card 44 tothe inter-interface connector 188 of one of the sharing bus interfacecards 48. At the inter-interface connector 188, the PRI OUT L signalline 462 connects to the PRI IN L signal line 202 depicted in FIG. 4.Thus, the signal line 462 transfers the PRI OUT signal from the busswitch state sequencer 302 on the control card 44 to the PAL 162 of oneof the sharing bus interface cards 48.

[0125]FIG. 7 is a logic diagram depicting the PAL 162 included in theinterface card 48. As with the logic diagrams of FIGS. 5 and 6, thelogic diagram of FIG. 7 illustrates the construction of the PAL 162 froma pedagogical viewpoint rather than conforming to the actualimplementation of the preferred embodiment. To increase comprehension,the logic circuitry depicted in FIG. 7 may omit or simplify certaindetails of the actual implementation of the PAL 162, e.g. detailsrelated to logic minimization and to the elimination of logic “hazards,”even logic hazards arising from transitions between phases of the SCSIbus protocol. Moreover, the logic diagram of FIG. 7 may also omitdetails related to circuit loading. However, while FIG. 7 may notprecisely depict the structure of the preferred embodiment, the detailedstructure of the portion of the interface card 48 residing in the PAL162 is expressly set forth in the description below. Accordingly, in thefollowing discussion of FIG. 7 all logic devices that are not expresslyreferred to by a reference number reside in the PAL 162. The PAL 162operates in conjunction with signals from the bus switch state sequencer302 and from the BSY and SEL signals on the SCSI bus to which itconnects as described below.

[0126] The signals exchanged between the PALs 162 on the sharinginterface cards 48 and the bus switch state sequencer 302 over the BUSIDLE L signal line 276, the CHANGE REQUEST L signal lines 272 and 272 b,the BUS CONNECTED L signal lines 274 and 274 b, and the daisy-chainedPRI OUT L signal lines 204 and 462 and the PRI IN L signal lines 202mediate selection and deselection of a particular sharing bus interfacecard 48 for exchanging signals with the control card 44. Both the BUSCONNECTED L signal line 274 b and the CHANGE REQUEST L signal line 272 bare wire-OR signal and are asserted low. Thus, assertion of the signalon the CHANGE REQUEST L signal line 272 of a sharing interface card 48informs the bus switch state sequencer 302 that one or more sharinginterface cards 48 is enabled to be selected for exchanging signals withthe control card 44. Similarly, assertion of the signal on the BUSCONNECTED L signal line 274 of a sharing interface card 48 informs thebus switch state sequencer 302 that one of the sharing interface cards48 is presently selected for exchanging signals with the control card44. The signals from the PALs 162 on the sharing interface cards 48 viathe signal lines 272 and 274 provide the bus switch state sequencer 302with the information necessary for it to drive the signal on its PRI OUTL signal line 462 that grants a requesting sharing bus interface card 48permission to become selected for exchanging signals with the controlcard 44. The daisy-chaining of the PRI OUT L signal lines 462 and 204and PRI IN L signal lines 202 through the sharing bus interface cards 48allows these cards 48 to determine among themselves which of the sharingbus interface cards 48 will be selected for exchanging signals with thecontrol card 44.

[0127] To prevent interface cards 48 from becoming enabled forexchanging signals between the control card 44 and the data bus 52-58 towhich they respectively connect (or becoming disabled from exchangingsuch signals) in the middle of a transaction on the shared data bus 58,the bus switch state sequencer 302 asserts the BUS IDLE L signal on thesignal line 276 only when it detects the BUS FREE phase of the SCSIprotocol. The PALs 162 in all the interface cards 48 receive the BUSIDLE L signal from the bus switch state sequencer 302 together withsignals on the BSY BUF L signal line 164 and SEL BUF L signal line 166of the bus 52-58 to which they connect. Consequently, the PAL 162 ineach interface card 48 receives signals indicating when the BUS FREEphase of the SCSI protocol exists on the shared data bus 58 and on thedata bus 52-58 to which it connects. The PAL 162 uses these signals toenable its interface card 48 for exchanging signals with the controlcard 44 (or disable the card 48 from exchanging such signals), i.e.changes the state of the latch which drives the BOARD SELECTED L signalline 212, only when it detects that the BUS FREE phase of the SCSI busprotocol exists simultaneously both on the data bus 52-58 to which itconnects and on the shared data bus 58. Thus, the interface cards 48become selected for exchanging signals between the control card 44 andthe data bus 52-58 to which they respectively connect or become disabledfrom exchanging such signals only when its PAL 162 detects the BUS FREEphase of the SCSI bus protocol on all of the relevant buses 52-58.

[0128] To use the bus switch 40 to gain access to the devices connectedto the shared data bus 58, an operator of one of the computers 62 closesthe contacts of the toggle switch 84. After expiration of a 2.2millisecond switch debounce time interval established by the monostablemultivibrator 176, the PAL 162 responds to the closure of the toggleswitch 84 by asserting the signal that it transmits on the CHANGEREQUEST L signal line 272 b.

[0129] Presentation of the asserted CHANGE REQUEST L signal on thesignal line 272 b by any of the PALs 162 informs the bus switch statesequencer 302 that one of the sharing interface cards 48 is enabled forselection to exchange signals with the control card 44. After the busswitch state sequencer 302 receives the assertion of the CHANGE REQUESTL signal on line 272 b, when the BUS CONNECTED L signal line 274 bbecomes negated (i.e. none of the sharing interface cards 48 areexchanging signals with the control card 44) and the BUS IDLE L signalis asserted (i.e. the shared data bus 58 is in the BUS FREE phase of theSCSI protocol), the bus switch state sequencer 302 then asserts thesignal it transmits on the SELECT L signal line 422 and latches it.Assertion of the signal on the SELECT L signal line 422 triggers themonostable multivibrator 424 to begin a four millisecond interval duringwhich the signal on the PRI OUT L signal line 462 remains negated. (Alsoduring this interval all devices connected to the shared data bus 58 arereset if the jumper 426 is installed on the control card 302.) At theend of the four millisecond interval, the bus switch state sequencer 302then asserts and latches the signal on the PRI OUT L signal line 462.

[0130] When the PAL 162 that asserted the signal on the CHANGE REQUESTEDL signal line 272 b receives the assertion of the signal on its PRI IN Lsignal line 202 and both of the relevant buses 52-58 are in their BUSFREE phase as described above, the PAL 162 then asserts and latches thesignal that it transmits to the bus switch state sequencer 302 on theBUS CONNECTED L signal line 274 b and negates the signal on the CHANGEREQUEST L signal line 272 b. The PAL 162 of the sharing interface card48 maintains its assertion of the signal on the BUS CONNECTED L signalline 274 b as long as the toggle switch 84 remains closed or thecomposite bus 52-58, 54-58 or 56-58 with which it is associated is notin the BUS FREE phase of the SCSI protocol. The bus switch statesequencer 302 responds to assertion of the BUS CONNECTED L signal line274 b by the PAL 162 of the sharing interface card 48 by unlatching theasserted signal on the SELECT L signal line 422 and negating thatsignal.

[0131] Contention among the sharing bus interface cards 48 for access tothe control card 44 is resolved using a daisy-chain of the PRI OUT Lsignal lines 204 and PRI IN L signal lines 202 through the sharing databus interface cards 48. Each of the PALs 162 in the sharing interfacecards 48 includes a second latch that inhibits retransmission of the PRIIN signal to the PRI OUT L signal line 204 while either the sharinginterface card 48 asserts the signal on the CHANGE REQUESTED L signalline 272 or is enabled for exchanging SCSI bus signals with the controlcard 44. Otherwise, this latch in the PAL 162 of the sharing interfacecard 48 allows the signal received by the sharing interface card 48 onthe PRI IN L signal line 202 to be transferred to PRI OUT L signal line204. Thus, while the toggle switch 84 connected to an interface card 48remains open, the PRI OUT signal received by that interface card 48 ismerely passed on to the next interface card 48 in the daisy-chain. Whenthe toggle switch 84 is closed, and the signal on the BOARD SELECT Lsignal line 212 is negated, and the signal on the PRI IN L signal line202 is negated, then the latch for inhibiting the PRI OUT signal in thePAL 162 of the sharing bus interface card 48 is set. Setting the latchforces the signal on the PRI OUT L signal line 204 of that interfacecard 48 remain negated. Negation of the signal on the PRI OUT L signalline 204 by an interface card 48 prevents any interface card 48 furtheralong the daisy-chain of PRI OUT L and PRI IN L signal lines 204 and 202from asserting the signal on the BUS CONNECTED L signal line 274 b. Ifan interface card 48 cannot assert the signal on the BUS CONNECTED Lsignal line 274 b, it cannot become selected for exchanging signals withthe control card 44.

[0132] Note that if the PAL 162 of a single-ended interface card 48receives a signal from the buffer 192 indicating that a differentialtype SCSI device is connected to the bus 52, 54, 56 or 58 to which itconnects, it immediately electronically isolates the circuits on theinterface card 48 from the bus 52, 54, 56 or 58 by negating the signalon the BOARD ENABLE L signal line 212. Since negation of the BOARDENABLE L signal line 212 prevents the LEDs on the housing for the busswitch 40 and at the shared bus-request box 76 from being illuminated,the inability to illuminate those LEDs is a positive indication that adifferential type SCSI device is connected to the bus 52, 54, 56 or 58to which the single-ended interface card 48 connects.

[0133] The PAL 162 is an MMI 16L8 assigned JEDEC type no. 2217 and isidentified as U17 in the table below. That table lists the referencenumbers of signal lines described in the preceding text and specifiesthe particular pin numbers of the various PALs to which that signal lineconnects. To adapt the PAL 162 for use in a single-ended interface card48, the voltage Vcc is applied to a BOARD DIF L signal line 472 depictedin FIG. 7. Signal Line Reference No. IC Pin No. U17 164 6 166 7 174 1183 9 184 8 193 2 202 11 204 12 212 16 272 15 274 14 276 4 278 5 472 3

[0134] Interface Card PAL IC U17 - Bus Selection Logic *D2217*F0* L000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1011011111111011111111111111111101111011111110111111111111111111 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111011111101111111111010100111111110111011111111111110101011 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111010111111011101111010101011111110111111101111111111101111 1111111011111110111111111111011111111110111111101111111101111111 1111111001111110111111111111111111111110111111101011111111111111 1111111011111110111110111111111111111110111111011111111110101011 1111111111111111111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111101111111111111111 1111111111111111111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1110111111111111111111111111111100000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000011111111111111111111111111111111 1111111111011111111111111111111000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000*C4BEA*

[0135] For the interface card 48 that connects to shared data bus 58, asstated previously both the PRI IN L signal line 202 and the SWITCH Lsignal line 182 connect to circuit ground. Thus, in accordance with thepreceding description of the operation of the interface cards 48connected to the sharing data buses 52, 54 and 56, the interface cardconnected to the shared bus 58 is always provided with a priority signalthat allows it to respond to the grounding of its SWITCH L signal line182 and is thereby always enabled to exchange signals between thecontrol card 44 and the shared data bus 58.

[0136] Differential SCSI Bus Interface Card

[0137] In place of one or more of the single-ended interface cards 48depicted in FIG. 4 that is adapted to exchange signals with asingle-ended SCSI bus 52, 54, 56 or 58, a differential interface cardcould be joined to the control card 44 at any of the interfaceconnectors 46 a or 46 b depicted in FIGS. 2 or 3. Under suchcircumstances, the bus switch 40 or 40′ would then be adapted toexchange signals between a differential SCSI bus and a single-ended SCSIbus, or between pairs of differential SCSI buses. Thus, by appropriatelychoosing the particular type of interface card 48, either single-endedor differential, for mating with the interface connectors 46 a or 46 bof the control card 44, the bus switch 40 may be easily and quicklyadapted to operate with any combination of single-ended and differentialSCSI data buses 52, 54, 56 and 58.

[0138] There are only a few differences between the single-endedinterface card 48 depicted in FIG. 4 and a differential interface card.First, each pair of receiving buffers 136 and transmitting buffers 138in each of the switched transceiver circuits 122-132 are replaced by asingle DS3695 integrated circuit, and the connections to the SCSI busconnector 60 is changed from the single-ended SCSI specification to thedifferential SCSI specification. This single DS3695 integrated circuit,which replaces each pair of buffers 136 and 138, receives or transmits adifferential SCSI bus signal in response to the same control signalsdepicted in FIG. 4 and described in the preceding text. In addition, ifthe differential interface card is located at either end of thedifferential SCSI bus, then it must also include differentialtermination resistor networks instead of the termination resistors 154and 156 depicted in FIG. 4.

[0139] With regard to the PAL 162, a differential interface card usesthe same PAL 162 as that described above for the single ended interfacecard 48. However, for the differential interface card, pin 3 of the PAL162 is connected to ground rather than to Vcc. While the PAL 162 stillreceives a BUS OK L signal via the BUS OK L signal line 193, that signalnow indicates that a single-ended SCSI bus device is connected to thedifferential interface card rather than the converse. To adapt thebuffer 192 to sense connection to a single-ended SCSI device, theresistor 196 that connects between the input of the buffer and circuitground is replaced by a series connected 1N4148 diode and resistor withthe resistor being connected to the input of the buffer 192 and theanode of the diode being connected to Vcc. In addition, the DIFFSENSline 194, that for the single-ended SCSI bus connects to pin 25 of thesingle ended SCSI bus connector 60, now connects to pin 21 of thedifferential SCSI bus connector.

[0140] Industrial Applicability

[0141] Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is purely illustrative and is not to be interpreted aslimiting. While the preceding description of the bus switch 40 hasinvolved exchanging signals between only three sharing data buses 52, 54and 56 and the shared data bus 58, in principle the invention is usefulwith a plurality of buses that is unlimited. Moreover, the generalfeatures disclosed herein, including the response to signals on the SCSIbus's BSY signal line and the arbitration-latches included in thebidirectional repeaters, appears applicable to other distributedarbitration digital data buses in which devices connect to the bus inparallel and none of the signal lines in the bus daisy-chains seriallythrough a sequence of devices that transmit and/or receive data over thebus.

[0142] Since the bus switch 40 may be easily adapted for exchangingsignals with either a single-ended SCSI bus or a differential SCSI bus,the bus switch 40 is useful simply as a repeater for exchanging signalsbetween one single-ended SCSI bus, e.g. shared data bus 58, and onedifferential SCSI bus, e.g. one of the sharing data buses 52, 54 or 56.Alternatively, because the length of the single-ended SCSI bus islimited by signal strength and noise coupling between the bus' severalsignal conductors, the bus switch 40 is also useful merely as a repeaterfor exchanging signals between two single-ended SCSI buses having atotal length that is greater than the 6 meter limitation of the SCSI busspecification.

[0143] The usefulness of the bus switch 40 as a repeater for exchangingsignals between SCSI buses is enhanced by its latching of both BSYsignal lines of the buses 52, 54, 56 or 58 included in the composite bus52-54, 52-56 or 52-58 during ARBITRATION and RESELECTION phases.Latching of both BSY signal lines 102 of both of the buses 52, 54, 56 or58 during these phases prevents wire-OR glitches on the BSY controlsignal line 102 in one of the buses 52, 54, 56 or 58, that are a normalevent in the SCSI bus' ARBITRATION and RESELECTION phases, frompropagating to the BSY control signal line 102 in the other bus 52, 54,56 or 58. It appears that this aspect of the bus switch 40 will allowits use as a repeater for coupling multiple SCSI buses into a singlecomposite bus having a total length greater than 25 meters. Failing tolatch the BSY signals on both buses during the ARBITRATION andRESELECTION phases will limit the total effective length of thecomposite bus to 25 meters including logic delays through a repeater orbus switch 40.

[0144] When used solely as a repeater between distributed arbitrationbuses whose length limitations arise from protocol considerations ratherthan signal quality considerations, e.g. differential SCSI buses, thebus switch 40 need include only the switched transceiver circuits 122and 124 for the BSY control signal lines 102 and for the SEL controlsignal lines 104 together with that portion of the circuitry on thecontrol card 44 which controls the transmission of the BSY and SELsignals by the bus switch 40, e.g. the circuitry which responds to theBSY, SEL and I/O SCSI bus signals. Such a minimal repeater omits all ofthe switched transceivers 126, 128, 130 and 132 and their associatedcontrol logic on the control card 44.

[0145] Consequently, without departing from the spirit and scope of theinvention, various alterations, modifications, and/or alternativeapplications of the invention will, no doubt, be suggested to thoseskilled in the art after having read the preceding disclosure.Accordingly, it is intended that the following claims be interpreted asencompassing all alterations, modifications, or alternative applicationsas fall within the true spirit and scope of the invention.

1-32. (Canceled)
 33. A network of computing devices comprising: a. adigital computer which is: i. capable of operating as an initiatordigital computing device for a Small Computer System Interface (“SCSI”)bus; and ii. connected in parallel to a first SCSI bus; b. a SCSI busrepeater which includes: i. a first interface that is connected to thefirst SCSI bus for receiving signals therefrom and supplying signalsthereto; ii. a second interface that is connected to a second SCSI busfor receiving signals therefrom and supplying signals thereto; and iii.a control circuit for controlling operation of the first and second SCSIbus interfaces that: A) permits a succession of SCSI bus phasesinitiated by an initiator digital computing device that is connected toeither of the SCSI buses to be concluded by a target digital computingdevice connected to the other SCSI bus, the succession of SCSI busphases ending upon occurrence of a bus free phase of the SCSI buses; andB) during the succession of SCSI bus phases, the control circuit,responsive to at least a first signal present at least one of the firstand second interfaces, controlling at least a second signal coupled fromat least one of the interfaces to the SCSI bus to which the interfaceconnects; and c. a target digital computing device connected in parallelto the second SCSI bus.
 34. The network of computing devices of claim 33wherein the control circuit of the SCSI bus repeater: during thesuccession of SCSI bus phases stores information which identifies theSCSI bus to which the digital computing device which initiated thesuccession of SCSI bus phases connects; and uses the information sostored in controlling a signal supplied from at least one of theinterfaces to one of the signal lines of the SCSI bus connected to theinterface other than the BSY signal line of that SCSI bus.
 35. Thenetwork of computing devices of claim 33 wherein the control circuit ofthe SCSI bus repeater stores information which identifies individualphases in the succession of SCSI bus phases.
 36. A network of computingdevices comprising: a. a digital computer which is connected in parallelto a sharing distributed arbitration digital data bus; b. a repeater forexchanging information between digital computing devices respectivelyconnected in parallel to the sharing distributed arbitration digitaldata bus or to a shared distributed arbitration digital data bus, saidrepeater interconnecting the shared and the sharing distributedarbitration digital data buses into a single, composite distributedarbitration digital data bus, said repeater including: i. a shared businterface circuit, connected to the shared distributed arbitrationdigital data bus, for receiving signals from and transmitting signals toa device connected to the shared distributed arbitration digital databus; ii. a sharing bus interface circuit, connected to the sharingdistributed arbitration digital data bus, for receiving signals from andtransmitting signals to a device connected to the sharing distributedarbitration digital data bus; and iii. control circuit, simultaneouslyconnected both to said shared bus interface circuit and to said sharingbus interface circuit, said control circuit responding to a plurality ofsignals on the shared and sharing distributed arbitration digital databuses for controlling both of said bus interface circuits during anexchange of information between devices connected to the compositedistributed arbitration digital data bus; and c. a digital computingdevice connected in parallel to the sharing distributed arbitrationdigital data bus.
 37. The network of computing devices of claim 36wherein information is exchanged between devices connected to thecomposite distributed arbitration digital data bus in accordance with abus protocol having a plurality of phases, said control circuit of saidrepeater also responding to an occurrence of a sequence of phases of thebus protocol.
 38. The network of computing devices of claim 37 whereinthe shared distributed arbitration digital data bus employs a firstsignaling convention for communicating signals thereon and the sharingdistributed arbitration digital data bus employs a second signalingconvention for communicating signals thereon, the first and secondsignaling conventions by which signals are communicated respectively onthe shared and sharing distributed arbitration digital data buses beingincompatible with each other.
 39. The network of computing devices ofclaim 37 wherein said shared bus interface circuit of said repeaterexchanges signals with a device in accordance with a first signalingconvention, said shared bus interface circuit of said repeaterindicating if a device employing a different signaling convention,incompatible with the first signaling convention of said shared businterface circuit of said repeater, is connected to the shareddistributed arbitration digital data bus.
 40. The network of computingdevices of claim 37 wherein said sharing bus interface circuit of saidrepeater exchanges signals with a device in accordance with a firstsignaling convention, said sharing bus interface circuit of saidrepeater indicating if a device employing a different signalingconvention, incompatible with the first signaling convention of saidsharing bus interface circuit, is connected to the sharing distributedarbitration digital data bus.
 41. A network of computing devicescomprising: a. a digital computer which is: i. capable of operating asan initiator digital computing device for a SCSI bus; and ii. connectedin parallel to a first SCSI bus; b. a repeater for exchanginginformation between an initiator digital computing device that connectsin parallel to the first SCSI bus and a target digital computing devicethat connects in parallel to a second SCSI bus, each SCSI busrespectively including signal lines via which the initiator and targetdigital computing device exchange signals, said repeater interconnectingthe first and the second SCSI buses into a single, composite SCSI bus,said repeater including: i. first SCSI bus interface circuit, connectedto the first SCSI bus, for receiving signals from and transmittingsignals to the initiator digital computing device; ii. second SCSI businterface circuit, connected to the second SCSI bus, for receivingsignals from and transmitting signals to a target digital computingdevice; and iii. control circuit, simultaneously coupled both to saidfirst SCSI bus interface circuit and to said second SCSI bus interfacecircuit, for controlling said first and second SCSI bus interfacecircuits during a sequence of SCSI bus phases that commences when aninitiator digital computing device, during a BUS FREE phase of the SCSIbus protocol, initiates an ARBITRATION phase of the SCSI protocol;during the sequence of SCSI bus phases commenced by the initiatordigital computing device the control circuit controlling the signalpresent on at least one signal line of either the first or second SCSIbuses responsive to a signal present on a different signal line ofeither the first or second SCSI buses; and the sequence of SCSI busphases ending whenever a BUS FREE phase of the SCSI bus protocol occurs;and c. a target digital computing device connected in parallel to thesecond SCSI bus.
 42. The network of computing devices of claim 41wherein the control circuit of the repeater stores information thatidentifies the SCSI bus to which the initiator device connects, thecontrol circuit responsive to the stored information controlling thesignal present on at least one signal line of either the first or secondSCSI buses other than a Select (“SEL”) signal line thereof.
 43. Thenetwork of computing devices of claim 41 wherein the control circuit ofthe repeater during one phase in the sequence of SCSI bus phases storesinformation for use during a subsequent phase in the sequence of SCSIbus phases.